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公开(公告)号：DE69824193T2
公开(公告)日：2005-05-19
申请号：DE69824193
申请日：1998-09-04
Applicant: INFINEON TECHNOLOGIES CORP
Inventor： FLECK G , MARTIN DANIEL
Abstract: The present invention relates to a data processing unit comprising a register file, a register load and store buffer connected to the register file, a single memory, and a bus having at least first and second word lines to form a double word wide bus coupling the register load and store buffer with said single memory. The register file at least two sets of registers whereby the first set of registers can be coupled with one of the word lines and the second set of registers can be coupled with the respective other word lines, a load and store control unit for transferring data from or to the memory.
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公开(公告)号：DE69803304T2
公开(公告)日：2002-05-02
申请号：DE69803304
申请日：1998-09-04
Applicant: INFINEON TECHNOLOGIES CORP
Inventor： FLECK G , ARNOLD D , HOLMER BRUCE , OKLOBDZIJA VOJIN , CHESTERS ERIC
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公开(公告)号：DE69915377T2
公开(公告)日：2005-02-24
申请号：DE69915377
申请日：1999-12-21
Applicant: INFINEON TECHNOLOGIES CORP
Inventor： WENZEL ANDREAS , CHESTERS ERIC , FLECK G , SHEEDY GARY
IPC: G01R31/3183 , G06F11/22 , G06F11/34 , G06F11/36 , G06F11/00
Abstract: An on-chip debug system includes a data band selector operable to transmit to an emulator the selected data bands generated by the selected components in an integrated circuit. The data band selector is directed by the emulator based upon instructions received from a host computer.
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Patent Agency Ranking
公开(公告)号：DE69821957T2
公开(公告)日：2004-12-09
申请号：DE69821957
申请日：1998-09-04
Applicant: INFINEON TECHNOLOGIES CORP
Inventor： FLECK G , MOLLER H , BAROR GIGY
Abstract: There are two pipelines, one for data instructions and the other for address instructions. A unit issues multiple instructions to the pipelines. Two sets of registers are connected to the pipelines respectively. The pipelines process data in parallel.
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公开(公告)号：DE69824193D1
公开(公告)日：2004-07-01
申请号：DE69824193
申请日：1998-09-04
Applicant: INFINEON TECHNOLOGIES CORP
Inventor： FLECK G , MARTIN DANIEL
Abstract: The present invention relates to a data processing unit comprising a register file, a register load and store buffer connected to the register file, a single memory, and a bus having at least first and second word lines to form a double word wide bus coupling the register load and store buffer with said single memory. The register file at least two sets of registers whereby the first set of registers can be coupled with one of the word lines and the second set of registers can be coupled with the respective other word lines, a load and store control unit for transferring data from or to the memory.
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公开(公告)号：DE69915377D1
公开(公告)日：2004-04-08
申请号：DE69915377
申请日：1999-12-21
Applicant: INFINEON TECHNOLOGIES CORP
Inventor： WENZEL ANDREAS , CHESTERS ERIC , FLECK G , SHEEDY GARY
IPC: G01R31/3183 , G06F11/22 , G06F11/34 , G06F11/36 , G06F11/00
Abstract: An on-chip debug system includes a data band selector operable to transmit to an emulator the selected data bands generated by the selected components in an integrated circuit. The data band selector is directed by the emulator based upon instructions received from a host computer.
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公开(公告)号：DE69821957D1
公开(公告)日：2004-04-01
申请号：DE69821957
申请日：1998-09-04
Applicant: INFINEON TECHNOLOGIES CORP
Inventor： FLECK G , MOLLER H , BAROR GIGY
Abstract: There are two pipelines, one for data instructions and the other for address instructions. A unit issues multiple instructions to the pipelines. Two sets of registers are connected to the pipelines respectively. The pipelines process data in parallel.
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公开(公告)号：DE69803304D1
公开(公告)日：2002-02-21
申请号：DE69803304
申请日：1998-09-04
Applicant: INFINEON TECHNOLOGIES CORP
Inventor： FLECK G , ARNOLD D , HOLMER BRUCE , OKLOBDZIJA VOJIN , CHESTERS ERIC
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