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    Data processing unit with interface for sharing registers by a processor and a coprocessor
    1.
    发明授权
    Data processing unit with interface for sharing registers by a processor and a coprocessor 有权
    具有用于由处理器和协处理器共享寄存器的接口的数据处理单元

    公开(公告)号：US6434689B2

    公开(公告)日：2002-08-13

    申请号：US18911198

    申请日：1998-11-09

    Applicant: INFINEON TECHNOLOGIES CORP

    Inventor： FLECK ROD G ,  ARNOLD ROGER D ,  HOLMER BRUCE ,  LEMAY DANIELLE G

    IPC: G06F9/38 ,  G06F15/00

    CPC classification number: G06F9/3897 ,  G06F9/3877 ,  G06F9/3885

    Abstract: An apparatus is described that comprises a data processing unit and at least one coprocessor. The data processing unit comprises a register file having registers, a memory, a plurality of execution units, a coprocessor interface for coupling the at least one coprocessor with the data processing unit, and a pipeline configuration for processing instructions having a fetch stage for fetching an instruction from the memory, a decode stage for decoding an operational code from the instruction, an execution stage for activating one of the execution units, and a write-back stage for God writing back from the execution unit. The data processing unit comprises read-and write-lines coupling the register file with the coprocessor for exchanging operands, at least one control line indicating that the coprocessor is busy, and a plurality of control lines from the decode stage for controlling the coprocessor which are operated upon detection of a coprocessor instruction. The coprocessor is using the registers from the register file during execution of the coprocessor instruction. The coprocessor comprises a decode unit for decoding the coprocessor instruction and a plurality of coprocessor execution units that share the decode unit, the decode unit selects one of the coprocessor execution units upon the coprocessor instruction, and the selected one of the coprocessor execution units performs the coprocessor instruction.

    Abstract translation: 描述了一种包括数据处理单元和至少一个协处理器的装置。 数据处理单元包括具有寄存器，存储器，多个执行单元，用于将至少一个协处理器与数据处理单元耦合的协处理器接口的寄存器文件，以及用于处理具有取出级的指令的流水线配置， 来自存储器的指令，用于从指令解码操作代码的解码级，用于激活执行单元中的一个的执行级，以及用于从执行单元写回的上一级的回写级。 数据处理单元包括将寄存器文件与协处理器耦合用于交换操作数的读和写行，指示协处理器忙的至少一个控制线以及来自用于控制协处理器的解码级的多条控制线 在检测到协处理器指令时进行操作。 在执行协处理器指令期间，协处理器正在使用寄存器文件中的寄存器。 协处理器包括用于解码协处理器指令的解码单元和共享解码单元的多个协处理器执行单元，解码单元在协处理器指令中选择一个协处理器执行单元，并且所选择的一个协处理器执行单元执行 协处理器指令

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