公开(公告)号：WO02054405A8

公开(公告)日：2002-09-06

申请号：PCT/US0147378

申请日：2001-12-04

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C7/12 ,  G11C

CPC classification number: G11C7/12

Abstract: A bitline architecture having bitlines with electrically controllable bitline lengths is described. The bitlines are provided with a switch which selectively couples or decouples local bitline segments of a bitline, depending on the need to execute the memory access. Bitlines with controllable bitline lengths can result in a reduction in power consumption without additional sense amplifiers or an additional metal layer.

Abstract translation: 描述了具有电可控位线长度的位线的位线架构。 位线提供有根据执行存储器访问的需要选择性地耦合或解耦位线的局部位线段的开关。 具有可控位线长度的位线可以导致功耗的降低，而不需要附加的读出放大器或额外的金属层。

公开(公告)号：JP2001273790A

公开(公告)日：2001-10-05

申请号：JP2001048272

申请日：2001-02-23

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： KIRIHATA TOSHIAKI ,  GABRIEL DANIEL

IPC: G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04

Abstract: PROBLEM TO BE SOLVED: To provide a memory device including a means coupling plural data storing cells, at least one redundant data storing cell, a redundant match detecting circuit, and a programmable fuse to a redundant match detecting circuit. SOLUTION: When a redundant match detecting circuit detects the prescribed condition set by a programmable fuse, a defective data is replaced by one redundant data storage region. Decoding is achieved by selecting an (e) fuse to be cut off by a data bus. Data bus, also, reads a state of the (e) fuse, and is used for guaranteeing that the (e) fuse is correctly cut off. Electric power is applied effectively to a selected (e) fuse while the data bus is shared to decode and verify the (e) fuse. Time-muliplex is used for transfer operation to reduce the number of communication channels between the (e) fuse and the redundant match detecting circuit, and transferring successively (e) fuse information to the redundant match detecting circuit can be performed. Actual time-multiplex operation for performing transfer is preferable to make 'enable' only after a chip is made a power source apply state.

公开(公告)号：JP2000353750A

公开(公告)日：2000-12-19

申请号：JP2000144824

申请日：2000-05-17

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： BRINTZINGER AXEL ,  KIRIHATA TOSHIAKI ,  NARAYAN CHANDRASEKHAR

IPC: H01L21/82 ,  H01H85/00 ,  H01L23/525 ,  H01H85/044

Abstract: PROBLEM TO BE SOLVED: To array a larger number of fuses densely by electrically connecting at least two fuses that contain a fusing part arrayed in a first level of a multi- layer semiconductor device, respectively. SOLUTION: Each fuse 13 contains a part 15 that is actually fused. The part 15 to be fused is arrayed in a first metal level M1. Like the other part of the fuse 13, the part 15 that is actually fused is made typically of a electrically conductive material, especially aluminum. A termination of each part 15 to be fused is connected to a connector bias 17 that connects that fuse 13 with a connector 19. A gate contact 23 is vertical to a direction of the fuse 13. The gate contact 23 can be connected to a ground that is common to all of existing fuse circuits. Therefore, fuse density is doubled without narrowing the fuse pitch.

公开(公告)号：JP2000251468A

公开(公告)日：2000-09-14

申请号：JP2000034052

申请日：2000-02-10

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： JI BRIAN ,  MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  HANSON DAVID

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/409

Abstract: PROBLEM TO BE SOLVED: To increase data speed or band width by arranging a pre-fetch circuit so that data speed among each hierarchy stage is all equalized substantially and controlling a latch so that the respective data speed at each hierarchy stage is all maintained. SOLUTION: Stages A-C have different data speed/signal time (data speed/bit) a, b, c respectively. Data speed at each stage is determined by data speed/signal path (selected by the number of signal path that is the number of pre-fetch). Pre-fetch is constituted between stages A-B of m>=int(a/b), pre-fetch is constituted between stages B-C of n>=int(b/c), and integers m, n are adjusted as desired. In order to vary pre-fetch depth at each stage, a pointer is designed so as to correspond to pre-fetch depth. A pointer signal is supplied by using a control circuit 214, the control circuit 214 latches continuously data made to synchronize with the latch included in a pre-fetch circuit, and timing is performed optimally.

公开(公告)号：JP2000235786A

公开(公告)日：2000-08-29

申请号：JP2000035922

申请日：2000-02-14

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  GERD FRANKOVSKI

IPC: G11C7/00 ,  G11C7/10 ,  G11C19/00 ,  G11C19/28 ,  H03K17/22 ,  H03K19/096

Abstract: PROBLEM TO BE SOLVED: To obtain a low voltage bus signalling architecture by providing a storage circuit which stores data after it is placed in a set state, an output circuit which connects stored data to an output by responding to an output strobe pulse and a reset circuit resetting the storage circuit by responding to the falling edge of the output strobe pulse. SOLUTION: This low voltage bus signalling architecture 20 has a driver 200 and a storage part 210. The driver 200 is an n-channel MOSFET inverter and inputs an input logic signal being on a line 203. The storage part 210 has a latch 250, an output circuit 260 and a reset circuit 270. The output circuit 260 connects stored data to an output DQ by responding to an output strobe pulse PNTo1. The reset circuit 270 precharges the storage part 210 via a first transistor 240 by responding to the falling edge of the pulse PNTo1.

公开(公告)号：JP2000222898A

公开(公告)日：2000-08-11

申请号：JP36513699

申请日：1999-12-22

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  DANIEL GABRIEL

IPC: G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To increase yield of chips while preventing signal contention of a sense amplifier using a high replacement flexibility redundancy and method. SOLUTION: Redundancy elements are integrated in at least two memory arrays which don't share the sense amplifiers. A defective row/column line in a first array or block is replaced with a redundant row/column line from its own redundancy. A corresponding row/column line whether defective or not is replaced in a second array or block which does not share sense amplifiers with the first block. The corresponding row/column line is replaced to mimic the redundancy replacement of the first block.

公开(公告)号：WO02054405A2

公开(公告)日：2002-07-11

申请号：PCT/US0147378

申请日：2001-12-04

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KIRIHATA TOSHIAKI ,  MUELLER GERHARD

IPC: G11C7/12 ,  G11C

CPC classification number: G11C7/12

Abstract: A bitline architecture having bitlines with electrically controllable bitline lengths is described. The bitlines are provided with a switch which selectively couples or decouples local bitline segments of a bitline, depending on the need to execute the memory access. Bitlines with controllable bitline lengths can result in a reduction in power consumption without additional sense amplifiers or an additional metal layer.

Abstract translation: 描述了具有电可控位线长度的位线的位线架构。 根据执行存储器访问的需要，位线提供有选择性地耦合或去耦合位线的局部位线段的开关。 位线长度可控的位线可以降低功耗，无需额外的读出放大器或额外的金属层。

公开(公告)号：JP2001068555A

公开(公告)日：2001-03-16

申请号：JP2000210177

申请日：2000-07-11

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH ,  LACHTRUPP DAVID ,  BRINTZINGER AXEL ,  GABRIEL DANIEL ,  KIRIHATA TOSHIAKI

IPC: H01L21/82 ,  H01H85/00 ,  H01H85/02 ,  H01H85/044 ,  H01H85/046 ,  H01L21/66 ,  H01L23/525 ,  H01L27/02

Abstract: PROBLEM TO BE SOLVED: To combine a laser actuation fuse with an electric starting fuse in order to increase total yield of product. SOLUTION: A plurality of different types of fuses 510, each serving a specified purpose, are arranged on a semiconductor integrated circuit wafer, such that a type of fuse can be actuated without missing the function of different types of fuses. A first type of fuse, e.g. a laser actuation fuse, is principally used for repairing a wafer level defect and a second type of fuse, e.g. an electric starting fuse, is used for repairing a defect found after an IC chip is mounted on a module and a stress is applied to the module during burn-in test. The module level defect is an unit cell trouble corrected normally by an electrically programmed fuse, in order to actuate a module level redundancy arrangement.

公开(公告)号：JP2000357394A

公开(公告)日：2000-12-26

申请号：JP2000131712

申请日：2000-04-28

Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

Inventor： KIRIHATA TOSHIAKI ,  GERHARD MUELLER

IPC: G11C11/401 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  H01L21/82 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit device containing a redundant metal line that can replace a metal line in a non-operation state for connecting circuit blocks thereto. SOLUTION: A conductive data line in a non-operation state is decoupled to a circuit block to which the line is connected because of defect or the other reason. A conductive data line having defect is replaced by a redundant line by coupling the same circuit block. A spare conductive block is not required. This semiconductor integrated circuit device is provided with a circuit block 5, a conductor 4 coupled electrically to the circuit block, the other conductor 2 adapted so as to be coupled electrically to the circuit block, a first means 16, 18 for discriminating whether the conductor 4 is in an operation state or a non-operation state, a first switch 14 decoupling electrically the conductor 4 from a circuit block 5, and a second switch 12 for coupling the other conductor 2 to the circuit block 5.

公开(公告)号：WO0193273A3

公开(公告)日：2002-08-08

申请号：PCT/US0117441

申请日：2001-05-31

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： MUELLER GERHARD ,  KIRIHATA TOSHIAKI ,  NETIS DMITRY

IPC: G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4094 ,  G11C11/4097 ,  G11C7/10

CPC classification number: G11C11/4094 ,  G11C7/12 ,  G11C7/18 ,  G11C8/12 ,  G11C11/4097

Abstract: There is provided a semiconductor memory device that includes: a plurality of memory cells arranged in at least two groups (102); at least one sense amplifier (SA); a first and a second multiplexer (MUXs); and at least one programmable control device (control circuit). Each multiplexer is adapted to couple at least one of the groups to the amplifier. The programmable control device is adapted to control the first and said second multiplexers. In one embodiment, the programmable control device is adapted to control the multiplexers independently.

Abstract translation: 提供了一种半导体存储器件，其包括：布置在至少两组（102）中的多个存储单元; 至少一个读出放大器（SA）; 第一和第二多路复用器（MUX）; 和至少一个可编程控制装置（控制电路）。 每个多路复用器适于将至少一个组耦合到放大器。 可编程控制装置适于控制第一和第二多路复用器。 在一个实施例中，可编程控制装置适于独立地控制多路复用器。