公开(公告)号：WO0229888A3

公开(公告)日：2002-08-29

申请号：PCT/US0127366

申请日：2001-08-31

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： DYER THOMAS W ,  KNORR ANDREAS ,  ECONOMIKOS LAERTIS ,  HALLE SCOTT

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10864 ,  H01L27/10891

Abstract: A Top Oxide Method is used to form an oxide layer over an array of vertical transistors as in a trench dynamic random access memory (DRAM) array with vertically stacked access metal oxide semiconductor field effect transistors (MOSFETs). The Top Oxide is formed by first forming the vertical devices with the pad nitride (16) remaining in place. Once the devices have been formed and the gate polysilicon (18) has been planarized down to the surface of the pad nitride, the pad nitride is stripped away leaving the tops of the gate polysilicon plugs extending above the active silicon surface. This pattern of polysilicon plugs defines the pattern over which the Top Oxide is deposited. The deposited Top Oxide (21) fills the regions between and on top of the polysilicon plugs. The Top Oxide is than planarized back to the tops of the polysilicon plugs so contacts can be made between the passing interconnects and the gates of the vertical devices. The Top Oxide layer serves to separate the passing interconnects from the active silicon thereby reducing capacitive coupling between the two levels and providing a robust etch-stop layer for the reactive ion etch (RIE) patterning of the subsequent interconnect level.

Abstract translation: 如在具有垂直堆叠的存取金属氧化物半导体场效应晶体管（MOSFET）的沟槽动态随机存取存储器（DRAM）阵列中，顶部氧化物方法用于在垂直晶体管阵列上形成氧化物层。 顶部氧化物通过首先形成具有衬垫氮化物（16）保持就位的垂直器件而形成。 一旦器件已经形成并且栅极多晶硅（18）已被平坦化到衬垫氮化物的表面，衬垫氮化物被剥离，留下栅极多晶硅插塞的顶部延伸到有源硅表面之上。 这种多晶硅插塞的图形定义了顶部氧化物沉积的图案。 沉积的顶部氧化物（21）填充多晶硅插塞之间和之上的区域。 顶部氧化物被平坦化回到多晶硅插塞的顶部，因此可以在通过的互连件和垂直装置的栅极之间形成接触。 顶部氧化物层用于将通过的互连与有源硅分离，从而减少两个电平之间的电容耦合，并提供用于后续互连电平的反应离子蚀刻（RIE）图案化的鲁棒蚀刻停止层。

公开(公告)号：WO0225729A2

公开(公告)日：2002-03-28

申请号：PCT/US0126232

申请日：2001-08-22

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： SEITZ MIHEL ,  KNORR ANDREAS ,  MCSTAY IRENE

IPC: H01L21/8242 ,  H01L21/20

CPC classification number: H01L27/10867 ,  H01L27/10864

Abstract: A high density plasma deposition process for eliminating or reducing a zipper-like profile of opened-up voids in a poly trench fill by controlling separation between a transfer gate and storage node in a vertical DRAM, comprising: etching a recess or trench into poly Si of a semiconductor chip; forming a pattern of SiN liner using a mask transfer process for formation of a single sided strap design; removing the SiN liner and etching adjacent collar oxide away from a top part of the trench; depositing a high density plasma (HDP) polysilicon layer in the trench by flowing either SiH4 or SiH4 + H2 in an inert ambient; employing a photores ist in the trench and removing the high density plasma polysilicon layer from a top surface of the semiconductor to avoid shorting in the gate conductor either by spinning on resist and subsequent chemical mechanical polishing or chemical mechanical downstream etchback of the polysilicon layer; and stripping the photoresist and depositing a top trench oxide by high density plasma.

Abstract translation: 一种高密度等离子体沉积工艺，用于通过控制垂直DRAM中的转移栅极和存储节点之间的分离来消除或减少多沟槽填充物中的开放空隙的拉链状轮廓，包括：将凹槽或沟槽蚀刻成多晶硅 的半导体芯片; 使用掩模转移工艺形成SiN衬垫的图案以形成单面带设计; 去除SiN衬垫并且蚀刻邻近的环氧化物远离沟槽的顶部; 通过在惰性环境中流过SiH4或SiH4 + H2，在沟槽中沉积高密度等离子体（HDP）多晶硅层; 在沟槽中采用光电池，并从半导体的顶表面去除高密度等离子体多晶硅层，以避免通过在抗蚀剂上旋转和随后的多晶硅层的化学机械抛光或化学机械下游回蚀而在栅极导体中短路; 并剥离光致抗蚀剂并通过高密度等离子体沉积顶部沟槽氧化物。

公开(公告)号：WO0199182A3

公开(公告)日：2002-04-18

申请号：PCT/US0119820

申请日：2001-06-21

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： WEBER STEFAN ,  RUF ALEXANDER ,  LIN CHENTING ,  KNORR ANDREAS

IPC: H01L21/285 ,  H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/28568 ,  H01L21/76807 ,  H01L21/76871 ,  H01L21/76877

Abstract: A method for forming metallizations for semiconductor devices, in accordance with the present invention, includes forming trenches (107) in a dielectric layer (104), depositing a single layer diffusion barrier (116) in the trenches, and without an air-brake, depositing a seed layer (118) of metal on the surface of the diffusion barrier. The trenches are then filled with metal (120). The metal adheres to the seed layer, which adheres to the diffusion barrier to provide many improvements in electrical characteristics as well as to reduce failures in the semiconductor devices.

Abstract translation: 根据本发明的用于形成用于半导体器件的金属化的方法包括在电介质层（104）中形成沟槽（107），在沟槽中沉积单层扩散阻挡层（116），并且没有空气制动， 在扩散阻挡层的表面上沉积金属种子层（118）。 然后用金属（120）填充沟槽。 金属粘附到种子层，其粘附到扩散阻挡层，以提供许多电特性的改进以及减少半导体器件的故障。

公开(公告)号：DE10214743A1

公开(公告)日：2004-11-04

申请号：DE10214743

申请日：2002-04-03

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KNORR ANDREAS ,  KUDELKA STEPHAN ,  MANDELMAN JACK ,  RAHN STEPHAN ,  TEWS HELMUT ,  WISE MICHAEL

IPC: H01L21/8242 ,  H01L29/94 ,  H01L27/108

公开(公告)号：DE10228691A1

公开(公告)日：2003-03-13

申请号：DE10228691

申请日：2002-06-27

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： KNORR ANDREAS ,  SEITZ MIHEL

IPC: H01L21/762 ,  H01L21/8242

Abstract: A method of providing isolation between element regions of a semiconductor memory device (200). Isolation trenches (211) are filled using several sequential anisotropic insulating material (216/226/230) HPD-CVD deposition processes, with each deposition process being followed by an isotropic etch back to remove the insulating material (216/226/230) from the isolation trench (211) sidewalls. A nitride liner (225) may be deposited after isolation trench (211) formation. A top portion of the nitride liner (225) may be removed prior to the deposition of the top insulating material (230) layer.