公开(公告)号：JP2000311991A

公开(公告)日：2000-11-07

申请号：JP2000080366

申请日：2000-03-22

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： TOBBEN DIRK ,  ALSMEIER JOHANN

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To obtain a method of forming a DRAM on a silicon chip, where an NMOSFET of a memory cell is provided in the center region of the silicon chip, a CMOSFET of a support circuit is provided in the peripheral region of the silicon chip. SOLUTION: A support circuit 100B is masked with an SiO2 film 20, and a polyside film 22 in a memory 100A is doped with N-type impurities. An SiN cap layer 26 is deposited thereon and covered with a patterned mask, the laminate is successively etched up to a gate insulating oxide film 12, a substrate 10 is doped with N-type impurities, and the source and drain region 32 of the memory 100A are formed. A sidewall dielectric spacer 34 is formed, and after an NMOSFET memory is nearly completed, a CMOSFET is formed in the supper circuit 100B.

公开(公告)号：WO0227797A3

公开(公告)日：2003-01-09

申请号：PCT/US0127074

申请日：2001-08-30

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： ALSMEIER JOHANN ,  GRUENING ULRIKE

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10876 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10861

Abstract: An improved sub 8F memory cell is disclosed. The sub 8F cell includes a trench capacitor (260) formed in a substrate; a shallow transistor trench (STT) (287) formed in the substrate; a transistor comprising a first diffusion region (213), the first diffusion region couples the transistor to the gate, a second diffusion region (214), the second diffusion region couples the transistor to a bit line, and a gate (212) serving as a word line, the gate includes a buried portion and a non-buried portion, wherein the buried portion of the gate occupies the shallow transistor trench.

Abstract translation: 公开了改进的子8F 2存储器单元。 子8F 2单元包括形成在衬底中的沟槽电容器（260） 形成在衬底中的浅晶体管沟槽（STT）（287）; 晶体管，包括第一扩散区域（213），第一扩散区域将晶体管耦合到栅极，第二扩散区域（214），第二扩散区域将晶体管耦合到位线，以及栅极（212） 一个字线，该栅极包括一个埋入部分和一个非埋置部分，其中栅极的埋入部分占据浅晶体管沟槽。

公开(公告)号：WO0201606A3

公开(公告)日：2002-05-30

申请号：PCT/US0120175

申请日：2001-06-25

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ALSMEIER JOHANN ,  RADEN CARL

IPC: H01L27/108

CPC classification number: H01L27/10841 ,  H01L27/10829

Abstract: A layout pattern for increasing the spacing between the deep trenches (79, 81) of one cell pair and the deep trenches of an adjacent cell pair in an array of semiconductor DRAM cell pairs each of which cell pairs share a common bitline contact (77) to bitlines (87, 89, 91) arranged in one direction and each of which cell pairs are coupled to gate conductors (83) arranged orthogonal to the bitlines. The layout pattern is formed by positioning the deep trenches of all of said pairs along alternate bitlines so they are offset from said bitlines along gate conductors in opposing directions. The deep trenches of all of the remaining bitlines are offset from said bitlines in opposing directions opposite to the opposing directions of said trenches along said alternate bitlines so as to form a herringbone pattern of cells.

Abstract translation: 一种用于增加一个单元对的深沟槽（79,81）和半导体DRAM单元对阵列中的相邻单元对的深沟槽之间的间隔的布局图案，每个单元对共享共同的位线触点（77） 到沿一个方向布置的位线（87,89,91），并且每个单元对耦合到与位线正交布置的栅极导体（83）。 通过将所有对的深沟槽沿着交替位线定位，使得它们沿相反方向沿着栅极导体偏离所述位线而形成布局图案。 所有剩余位线的深沟槽在与所述沟槽沿着所述替代位线的相反方向相反的相对方向上偏离所述位线，以便形成单元格的人字形图案。

公开(公告)号：WO0191179A3

公开(公告)日：2002-04-11

申请号：PCT/US0116140

申请日：2001-05-18

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ALSMEIER JOHANN ,  LAROSA GIUSEPPE ,  LUKAITIS JOSEPH ,  REAMGARAJAN RAJESH

IPC: H01L21/762

CPC classification number: H01L21/76229 ,  H01L21/76237

Abstract: Semiconductor device and method of manufacturing the same are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. After formation of the oxide liner, first regions of the semiconductor substrate are masked, leaving second regions thereof exposed. N-type devices are to be formed in the first regions and p-type devices are to be formed in the second regions. N-type ions may then be implanted into sidewalls of the trenches in the second regions. The mask is stripped and formation of the semiconductor device may be carried out in a conventional manner. The n-type ions are preferably only implanted into sidewalls where PMOSFETs are formed.

Abstract translation: 提供半导体装置及其制造方法。 在半导体衬底中形成沟槽。 优选在沟槽的表面上形成薄的氧化物衬垫。 在形成氧化物衬垫之后，掩模半导体衬底的第一区域，使第二区域暴露。 在第一区域中将形成N型器件，并且在第二区域中将形成p型器件。 然后可以将N型离子注入到第二区域中的沟槽的侧壁中。 剥离掩模，并且可以以常规方式进行半导体器件的形成。 n型离子优选仅被注入形成PMOSFET的侧壁。

公开(公告)号：DE60134848D1

公开(公告)日：2008-08-28

申请号：DE60134848

申请日：2001-05-18

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： ALSMEIER JOHANN ,  LAROSA GIUSEPPE ,  LUKAITIS JOSEPH ,  RENGARAJAN RAJESH

IPC: H01L21/762

Abstract: A semiconductor device and method of manufacturing the same are provided. A trench is formed in a semiconductor substrate. A thin oxide liner is preferably formed on surfaces of the trench. After formation of the oxide liner, first regions of the semiconductor substrate are masked, leaving second regions thereof exposed. N-type devices are to be formed in the first regions and p-type devices are to be formed in the second regions. N-type ions may then be implanted into sidewalls of the trenches in the second regions. The mask is stripped and formation of the semiconductor device may be carried out in a conventional manner. The n-type ions are preferably only implanted into sidewalls where PMOSFETs are formed.