公开(公告)号：WO0195382A3

公开(公告)日：2002-08-29

申请号：PCT/US0118539

申请日：2001-06-07

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CLEVENGER LAWRENCE A ,  HSU LOUIS ,  STEPHENS JEREMY K ,  WISE MICHAEL

IPC: H01L21/76 ,  H01L21/285 ,  H01L21/304 ,  H01L21/306 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L21/31053 ,  H01L21/28525 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/7684

Abstract: A method of using diamond or a diamond-like carbon layer as a polish-stop for patterning a metal level into an inter-level dielectric substrate using a damascene process flow. The diamond or diamond-like carbon layer is deposited onto the surface of the substrate before patterning the metal level. A protective layer is then deposited over the diamond or diamond-like carbon polish-stop layer, wherein such protective layer may act as an additional polish-stop layer. Together, the diamond or diamond-like carbon polish-stop layer and the protective layer are used as a hard-mask for patterning the trenches that will become the metal features, wherein such protective layer protects the diamond or diamond-like carbon polish-stop layer during the patterning process. After deposition of a conductive metal layer, the dielectric substrate is polished to remove excess conductive material, as well as topography. In the polishing process, the diamond or diamond-like carbon polish-stop layer and any remaining protective layer are used as polish-stop layers. The diamond or diamond-like carbon polish-stop layer allows for an improved planar surface, thereby resulting in an sufficient decrease in topography at the surface of the inter-level dielectric.

Abstract translation: 使用金刚石或类金刚石碳层作为抛光停止件的方法，其使用镶嵌工艺流程将金属层图案化成层间电介质基板。 在图案化金属层之前，将金刚石或类金刚石碳层沉积在基板的表面上。 然后将保护层沉积在金刚石或类金刚石碳抛光层上，其中这种保护层可以用作另外的抛光停止层。 一起使用金刚石或类金刚石碳抛光层和保护层作为用于图案化将成为金属特征的沟槽的硬掩模，其中这种保护层保护金刚石或类金刚石碳抛光 在图案化过程中。 在沉积导电金属层之后，电介质基底被抛光以除去过量的导电材料以及形貌。 在抛光过程中，将金刚石或类金刚石碳抛光层和任何剩余的保护层用作抛光 - 停止层。 金刚石或类金刚石碳抛光层允许改进的平面表面，从而导致层间电介质表面的形貌的充分降低。

公开(公告)号：WO02054457A2

公开(公告)日：2002-07-11

申请号：PCT/US0143904

申请日：2001-11-14

Applicant: INFINEON TECHNOLOGIES CORP

Inventor： LIAN JINGYU ,  LIN CHENTING ,  NAGEL NICOLAS ,  WISE MICHAEL

IPC: H01L21/02

CPC classification number: H01L28/75 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  Y10S257/906 ,  Y10S257/908

Abstract: A multi-layer electrode (246) and method of fabrication thereof in which a conductive region (244) is separated from a barrier layer (222) by a first conductive liner (240) and a second conductive liner (242). First conductive layer (240) comprises Pt, and second conductive liner (242) comprises a thin layer of conductive oxide. The multi-layer electrode (246) prevents oxygen diffusion through the top conductive region (244) and reduces material variation during electrode patterning.

Abstract translation: 一种多层电极（246）及其制造方法，其中通过第一导电衬垫（240）和第二导电衬套（242）将导电区域（244）与阻挡层（222）分离。 第一导电层（240）包括Pt，并且第二导电衬垫（242）包括导电氧化物的薄层。 多层电极（246）防止氧扩散通过顶部导电区域（244）并且减少电极图案化期间的材料变化。

公开(公告)号：DE10214743A1

公开(公告)日：2004-11-04

申请号：DE10214743

申请日：2002-04-03

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： KNORR ANDREAS ,  KUDELKA STEPHAN ,  MANDELMAN JACK ,  RAHN STEPHAN ,  TEWS HELMUT ,  WISE MICHAEL

IPC: H01L21/8242 ,  H01L29/94 ,  H01L27/108

公开(公告)号：DE60132435D1

公开(公告)日：2008-03-06

申请号：DE60132435

申请日：2001-03-12

Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

Inventor： CLEVENGER LARRY ,  HSU LOUIS L ,  NARAYAN CHANDRASEKHAR ,  STEPHENS JEREMY K ,  WISE MICHAEL

IPC: H01L23/525 ,  H01L21/768

Abstract: An electrical fuse structure comprises a semiconductor substrate; at least one electrically insulating layer over the semiconductor substrate having a portion thereof containing electrical wiring and another, adjacent portion thereof substantially free of electrical wiring; optionally, a further electrically insulating layer over the at least one electrically insulating layer. The electrically insulating layer(s) have a depression formed over the portion substantially free of electrical wiring, with the depression having a lower surface level than an adjacent portion of the electrically insulating layer. The fuse structure also includes a fuse insulator disposed over the depression and a fuse over the fuse insulator. Preferably, the fuse insulator is disposed only in the depression to elevate the fuse to the same level as the adjacent portion of the electrically insulating layer. The fuse structure may have a single layer or comprise alternating layers having different degrees of reflectivity to a laser beam, such as alternating layers of silicon oxide and silicon nitride. The preferred fuse structure comprises an electrically and thermally resistive fuse insulator in the depression, such that the fuse insulator substantially prevents heat of an energy beam directed at the fuse from being transmitted to the semiconductor substrate. More preferably, the fuse formed has a width less that that of the fuse insulator. The fuse structure may further include additional wiring over the electrical insulating layer at the same level as the fuse.