-
公开(公告)号:WO0124228A3
公开(公告)日:2002-03-14
申请号:PCT/US0026355
申请日:2000-09-25
Applicant: INPUT OUTPUT INC
Inventor: YU LIANZHONG , GOLDBERG HOWARD D , YU DULI
IPC: G02B26/10 , B81B3/00 , B81B7/00 , B81C1/00 , B81C99/00 , C23F1/02 , G01P9/04 , G02B26/08 , G03F7/20 , B44C1/22 , G03F7/00 , H01L21/306
CPC classification number: B81C1/00142 , B81B2201/042 , B81B2203/0315 , B81C1/00896 , B81C2203/0118 , B81C2203/036 , G02B26/0816
Abstract: A micro machined structure includes one or more temporary bridges for temporarily coupling the micro machined structure to a support structure.
Abstract translation: 微加工结构包括用于将微加工结构临时耦合到支撑结构的一个或多个临时桥。
-
公开(公告)号:CA2384889C
公开(公告)日:2010-05-04
申请号:CA2384889
申请日:2000-09-25
Applicant: INPUT OUTPUT INC
Inventor: YU LIANZHONG , GOLDBERG HOWARD D , YU DULI
IPC: B81C1/00 , G02B26/10 , B81B3/00 , B81B7/00 , B81C99/00 , C23F1/02 , G01L1/00 , G01P9/04 , G01P15/18 , G02B26/08 , G03F7/00 , G03F7/20 , H01L21/306
Abstract: A micro machined structure includes one or more temporary bridges for temporarily coupling the micro machined structure to a support structure.
-
公开(公告)号:NO20026151A
公开(公告)日:2003-02-14
申请号:NO20026151
申请日:2002-12-20
Applicant: INPUT OUTPUT INC
Inventor: SELVAKUMAR ARJUN , YU DULI , YU LIANZHONG , JONES BEN W
IPC: B81B3/00 , B81C1/00 , G01P15/08 , G01P15/125 , G01V1/18
CPC classification number: G01V1/181 , B81B3/0072 , B81B7/0016 , B81B2201/0235 , B81B2203/0109 , B81B2203/0163 , B81B2203/053 , G01P15/0802 , G01P15/125 , G01P2015/0814
-
公开(公告)号:NO20025744D0
公开(公告)日:2002-11-29
申请号:NO20025744
申请日:2002-11-29
Applicant: INPUT OUTPUT INC
Inventor: RIED ROBERT P , SELVAKUMAR ARJUN , GOLDBERG HOWARD D , SCHMIDT MARTIN A , YU LIANZHONG
IPC: G01P15/08 , G01P15/125 , G01V1/18 , G01P
-
公开(公告)号:AU6508401A
公开(公告)日:2001-12-11
申请号:AU6508401
申请日:2001-05-29
Applicant: INPUT OUTPUT INC
Inventor: RIED ROBERT P , SELVAKUMAR ARJUN , GOLDBERG HOWARD D , SCHMIDT MARTIN A , YU LIANZHONG
IPC: G01P15/08 , G01P15/125 , G01V1/18 , G01P15/00
-
公开(公告)号:NO20014460A
公开(公告)日:2001-11-16
申请号:NO20014460
申请日:2001-09-14
Applicant: INPUT OUTPUT INC
Inventor: RUSHEFSKY LARRY , SIGMAR AXEL , GOLDBERG HOWARD D , STALNAKER W MARC , RINNE RAY , BALDERES DEMETRIOS , LEMKE AL , IP MATTHEW , BEHN LAWRENCE P , DOMAGALSKI KLAUS , YU LIANZHONG , SELVAKUMAR ARJUN , YU DULI , MARSH JAMES L , MAXWELL PETER , MORGAN DAVID , BUIE THOMAS , FABER KEES , ALTMAN SJOERD , LAROO RICHARD
IPC: G01P21/00 , G01D11/24 , G01D18/00 , G01H1/00 , G01L27/00 , G01N1/02 , G01P1/02 , G01P15/08 , G01P15/125 , G01P15/13 , G01V1/047 , G01V1/053 , G01V1/104 , G01V1/18 , G01V1/40 , H01L21/60 , H01L29/84 , H05K5/00 , B65D85/38 , G01D21/00
CPC classification number: G01P1/023 , B81B3/001 , B81B3/0072 , B81B7/0016 , B81B2201/0235 , G01D11/245 , G01D18/008 , G01N2001/021 , G01P15/0802 , G01P15/13 , G01P21/00 , G01V1/047 , G01V1/053 , G01V1/104 , G01V1/181 , G01V1/186 , H01L2224/48472 , H01L2924/0002 , H01L2924/00
-
公开(公告)号:CA2378725A1
公开(公告)日:2001-01-18
申请号:CA2378725
申请日:2000-07-13
Applicant: INPUT OUTPUT INC
Inventor: YU DULI , GOLDBERG HOWARD D , RIED ROBERT P , YU LIANZHONG
IPC: G02B26/10 , B81B3/00 , B81C1/00 , C23F1/02 , G01P9/04 , G02B26/08 , G03F7/20 , G06V30/224 , C23F1/00 , G02B26/00 , G01P15/135 , G03F7/26
Abstract: The present invention provides merged-mask processes for fabricating micro- machined devices in general and mirrored assemblies for use in optical scanning devices in particular. The process includes (a) providing a substra te having a predetermined thickness; (b) applying a first masking layer on a first portion of the substrate and a second masking layer on a second portio n of the substrate, said second masking layer being at least as thick as the first masking layer; (c) etching a portion of the second masking layer to provide a first exposed portion of the substrate; (d) etching the first exposed portion of the substrate to a first depth; (e) etching the second masking layer to provide a second exposed portion of the substrate; and (f) etching simultaneously the first exposed portion of the substrate to a secon d depth and the second exposed portion of the substrate to a first depth. The process further comprises patterning the first masking layer before applying the second masking layer to provide the second portion of the substrate for etching and etching the first masking layer to expose the second portion of the substrate. The first and second masking layers are applied prior to etching the substrate.
-
公开(公告)号:AU3631700A
公开(公告)日:2000-10-04
申请号:AU3631700
申请日:2000-03-17
Applicant: INPUT/OUTPUT INC
Inventor: RUSHEFSKY LARRY , SIGMAR AXEL , GOLDBERG HOWARD D , STALNAKER W MARC , RINNE RAY , BALDERES DEMETRIOS , LEMKE AL , IP MATTHEW , BEHN LAWRENCE P , DOMAGALSKI KLAUS , YU LIANZHONG , SELVAKUMAR ARJUN , YU DULI , MARSH JAMES L , MAXWELL PETER , MORGAN DAVID , BUIE THOMAS , FABER KEES , ALTMAN SJOERD , LAROO RICHARD
IPC: G01P21/00 , G01D11/24 , G01D18/00 , G01H1/00 , G01L27/00 , G01N1/02 , G01P1/02 , G01P15/08 , G01P15/125 , G01P15/13 , G01V1/047 , G01V1/053 , G01V1/104 , G01V1/18 , G01V1/40 , H01L21/60 , H01L29/84 , H05K5/00 , G01D21/00 , B65D85/38
Abstract: An accelerometer (305) for measuring seismic data. The accelerometer (305) includes an integrated vent hole for use during a vacuum sealing process and a balanced metal pattern for reducing cap wafer bowing. The accelerometer (305) also includes a top cap press frame recess (405) and a bottom cap press frame recess (420) for isolating bonding pressures to specified regions of the accelerometer (305). The accelerometer (305) is vacuum-sealed and includes a balanced metal pattern (730) to prevent degradation of the performance of the accelerometer (305). A dicing process is performed on the accelerometer (305) to isolate the electrical leads of the accelerometer (305). The accelerometer (305) further includes overshock protection bumpers (720) and patterned metal electrodes to reduce stiction during the operation of the accelerometer (305).
-
公开(公告)号:DE60034451D1
公开(公告)日:2007-05-31
申请号:DE60034451
申请日:2000-03-17
Applicant: INPUT OUTPUT INC
Inventor: RUSHEFSKY LARRY , SIGMAR AXEL , GOLDBERG HOWARD D , STALNAKER W MARC , RINNE RAY , BALDERES DEMETRIOS , LEMKE AL , IP MATTHEW , BEHN LAWRENCE P , DOMAGALSKI KLAUS , YU LIANZHONG , SELVAKUMAR ARJUN , YU DULI , MARSH JAMES L , MAXWELL PETER , MORGAN DAVID , BUIE THOMAS , FABER KEES , ALTMAN SJOERD , LAROO RICHARD
IPC: G01D11/24 , G01P21/00 , G01D18/00 , G01D21/00 , G01H1/00 , G01L27/00 , G01N1/02 , G01P1/02 , G01P15/00 , G01P15/08 , G01P15/125 , G01P15/13 , G01V1/047 , G01V1/053 , G01V1/104 , G01V1/18 , G01V1/40 , H01L21/60 , H01L29/84 , H05K5/00
Abstract: An accelerometer (305) for measuring seismic data. The accelerometer (305) includes an integrated vent hole for use during a vacuum sealing process and a balanced metal pattern for reducing cap wafer bowing. The accelerometer (305) also includes a top cap press frame recess (405) and a bottom cap press frame recess (420) for isolating bonding pressures to specified regions of the accelerometer (305). The accelerometer (305) is vacuum-sealed and includes a balanced metal pattern (730) to prevent degradation of the performance of the accelerometer (305). A dicing process is performed on the accelerometer (305) to isolate the electrical leads of the accelerometer (305). The accelerometer (305) further includes overshock protection bumpers (720) and patterned metal electrodes to reduce stiction during the operation of the accelerometer (305).
-
公开(公告)号:DE60016928D1
公开(公告)日:2005-01-27
申请号:DE60016928
申请日:2000-07-13
Applicant: INPUT OUTPUT INC
Inventor: YU LIANZHONG , RIED P , GOLDBERG D , YU DULI
IPC: G02B26/10 , B81B3/00 , B81C1/00 , C23F1/02 , G01P9/04 , G02B26/08 , G03F7/20 , G06V30/224 , G01P15/135 , G02B26/00 , C23F1/00 , G03F7/26 , G03F7/00
Abstract: The present invention provides merged-mask processes for fabricating micromachined devices in general and mirrored assemblies for use in optical scanning devices in particular. A method of fabricating a three dimensional structure, comprising, providing a substrate, applying a layer of a first masking material onto the substrate, applying a layer of a second masking material onto the layer of the first masking material, patterning the layer of the second masking material, applying a layer of a third masking material onto the portions not covered by the patterned layer of the second masking material, the layer of the third masking material is at least as thick as the combined thickness of the layers of the first and second masking materials, patterning the layers of the first and third masking materials, etching the exposed portions of the substrate, etching the exposed portions of the layers of the first and third masking materials and etching the exposed portions of the substrate.
-
-
-
-
-
-
-
-
-