公开(公告)号：US20250015084A1

公开(公告)日：2025-01-09

申请号：US18763440

申请日：2024-07-03

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Fei Zhao

IPC: H01L27/092 ,  H01L21/225 ,  H01L21/762 ,  H01L29/06 ,  H01L29/161 ,  H01L29/24 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A semiconductor device and a method for manufacturing the same. The semiconductor device comprises an n-channel GAA transistor and a p-channel GAA transistor, which are spaced apart. Each of the n-channel GAA transistor and the p-channel GAA transistor comprises a source, a drain, and at least one nanostructure layer located between the source and the drain. The p-channel GAA transistor further comprises a gate stack structure and a gate sidewall. In the p-channel GAA transistor, the at least one nanostructure layer comprises a channel portion that is covered by the gate stack structure and a connecting portion that is covered by the gate sidewall, and germanium content in the channel portion is greater than germanium content in the connecting portion and is greater than germanium content in the at least one nanostructure layer of the n-channel GAA transistor.

公开(公告)号：US20230326965A1

公开(公告)日：2023-10-12

申请号：US18087347

申请日：2022-12-22

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Anlan Chen ,  Fei Zhao ,  Xiaohong Cheng ,  Huaxiang Yin ,  Jun Luo ,  Wenwu Wang

IPC: H01L29/786 ,  H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device and a method for manufacturing the same. The semiconductor device includes: a first gate-all-around (GAA) transistor disposed in the first region, including a first nanowire or nanosheet of at least one first layer, the at least one first layer and the substrate form a first group, among which all pairs of adjacent layers are separated by first distances, respectively; and a second GAA transistor disposed in the second region, including a second nanowire or nanosheet of at least two second layers, the at least two second layers and the substrate form a second group, among which the second layers are separated by second distances, respectively; where a minimum first distance is greater than a maximum second distance, and a quantity of the at least one first layer is less than a quantity of the at least two second layers.

公开(公告)号：US20240213336A1

公开(公告)日：2024-06-27

申请号：US18522198

申请日：2023-11-28

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Fei Zhao

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A gate-all-around transistor is provided, including: a semiconductor substrate, a nanostructure, a gate stack structure and a gate length defining structure. In a length direction of the nanostructure, each layer of nanostructure includes a source region, a drain region, and a channel region between the two. Materials of the source region and drain region include a first metal semiconductor compound. The gate stack structure surrounds the channel region. In a length direction of the gate stack structure, a sidewall of the gate stack structure is recessed relative to a sidewall of the channel region to form a recess, and the gate length defining structure is filled in the recess. The gate length defining structure is made of a second metal semiconductor compound, and a semiconductor material for making the second metal semiconductor compound is different from that for making the first metal semiconductor compound.

公开(公告)号：US20230261050A1

公开(公告)日：2023-08-17

申请号：US18059960

申请日：2022-11-29

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Yongliang Li ,  Xiaohong Cheng ,  Fei Zhao ,  Jun Luo ,  Wenwu Wang

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/6681 ,  H01L29/7831 ,  H01L29/785

Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes: a substrate and a channel portion. The channel portion includes a first portion including a fin-shaped structure protruding with respect to the substrate and a second portion located above the first portion and spaced apart from the first portion. The second portion includes one or more nanowires or nanosheets spaced apart from each other. Source/drain portions are arranged on two opposite sides of the channel portion in a first direction and in contact with the channel portion. A gate stack extends on the substrate in a second direction intersecting with the first direction, so as to intersect with the channel portion.