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公开(公告)号:US20250006822A1
公开(公告)日:2025-01-02
申请号:US18708028
申请日:2023-11-27
Inventor: Na Zhou , Junjie Li , Jianfeng Gao , Tao Yang , Junfeng Li , Jun Luo
IPC: H01L29/66 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/786
Abstract: A method for manufacturing a gate-all-around TFET device. The method comprises: forming, on a substrate, a channel stack comprising channel layer(s) and sacrificial layer(s) that alternate with each other; forming, on the substrate, a dummy gate astride the channel stack; forming a first spacer at a surface of the dummy gate; etching the sacrificial layer(s) to form recesses on side surfaces of the channel stack; forming second spacers in the recesses, respectively; fabricating a source and a drain separately, where a region for fabricating the source is shielded by a dielectric material when fabricating the drain, and a region for fabricating the drain is shielded by another dielectric material when fabricating the source; etching the dummy gate and the sacrificial layer(s) to form a space for a surrounding gate; and fabricating a surrounding dielectric-metal gate in the space.
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公开(公告)号:US20240191168A1
公开(公告)日:2024-06-13
申请号:US18529820
申请日:2023-12-05
Inventor: Junjie Li , Na Zhou , Enxu Liu , Jianfeng Gao , Junfeng Li , Jun Luo , Wenwu Wang
CPC classification number: C12M25/04 , G03F7/70383
Abstract: A method for manufacturing a nanostructure and a nanostructure are disclosed. The method for manufacturing the nanostructure includes first alternately and periodically stacking a first material layer and a second material layer on a substrate to form a stacked layer, then forming a slot pattern on an upper surface of the stacked layer and etching the stacked layer to an upper surface of the substrate to transfer the slot pattern to the stacked layer, filling the slot pattern in the stacked layer with a molding material, and removing the first material layer or the second material layer left in the stacked layer, so as to form nanopores arranged in an array in the stacked layer.
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