公开(公告)号：US11127783B2

公开(公告)日：2021-09-21

申请号：US16177999

申请日：2018-11-01

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong Zhu ,  Junjie Li ,  Chao Zhao

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L43/10

Abstract: A Magnetic Random Access Memory (MRAM), a method of manufacturing the same, and an electronic device including the same are provided. The MRAM includes a substrate, an array of memory cells arranged in rows and columns, bit lines, and word lines. The memory cells each include a vertical switch device and a magnetic tunnel junction on the switch device and electrically connected to a first terminal of the switch device. An active region of the switch device at least partially includes a single-crystalline semiconductor material. Each of the memory cell columns is disposed on a corresponding bit line, and a second terminal of each of the respective switch devices in the memory cell column is electrically connected to the corresponding bit line. Each of the word lines is electrically connected to a control terminal of the respective switch devices of the respective memory cells in a corresponding memory cell row.

公开(公告)号：US20190157345A1

公开(公告)日：2019-05-23

申请号：US16177999

申请日：2018-11-01

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Huilong ZHU ,  Junjie Li ,  Chao Zhao

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/02

Abstract: A Magnetic Random Access Memory (MRAM), a method of manufacturing the same, and an electronic device including the same are provided. The MRAM includes a substrate, an array of memory cells arranged in rows and columns, bit lines, and word lines. The memory cells each include a vertical switch device and a magnetic tunnel junction on the switch device and electrically connected to a first terminal of the switch device. An active region of the switch device at least partially includes a single-crystalline semiconductor material. Each of the memory cell columns is disposed on a corresponding bit line, and a second terminal of each of the respective switch devices in the memory cell column is electrically connected to the corresponding bit line. Each of the word lines is electrically connected to a control terminal of the respective switch devices of the respective memory cells in a corresponding memory cell row.

公开(公告)号：US20240191168A1

公开(公告)日：2024-06-13

申请号：US18529820

申请日：2023-12-05

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Junjie Li ,  Na Zhou ,  Enxu Liu ,  Jianfeng Gao ,  Junfeng Li ,  Jun Luo ,  Wenwu Wang

IPC: C12M1/12 ,  G03F7/00

CPC classification number: C12M25/04 ,  G03F7/70383

Abstract: A method for manufacturing a nanostructure and a nanostructure are disclosed. The method for manufacturing the nanostructure includes first alternately and periodically stacking a first material layer and a second material layer on a substrate to form a stacked layer, then forming a slot pattern on an upper surface of the stacked layer and etching the stacked layer to an upper surface of the substrate to transfer the slot pattern to the stacked layer, filling the slot pattern in the stacked layer with a molding material, and removing the first material layer or the second material layer left in the stacked layer, so as to form nanopores arranged in an array in the stacked layer.

公开(公告)号：US11456218B2

公开(公告)日：2022-09-27

申请号：US17004173

申请日：2020-08-27

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Guilei Wang ,  Henry H Radamson ,  Zhenzhen Kong ,  Junjie Li ,  Jinbiao Liu ,  Junfeng Li ,  Huaxiang Yin

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/088 ,  H01L29/78

Abstract: A semiconductor device and a method for manufacturing the semiconductor device. Multiple stacks and an isolation structure among the multiple stacks are formed on a substrate. Each stack includes a first doping layer, a channel layer and a second doping layer. For each stack, the channel layer is laterally etched from at least one sidewall of said stack to form a cavity located between the first doping layer and the second doping layer, and a gate dielectric layer and a gate layer are formed in the cavity. A first sidewall of each stack is contact with the isolation structure, and the at least one sidewall does not include the first side wall. Costly high-precision etching is not necessary, and therefore a device with a small size and a high performance can be achieved with a simple process and a low cost. Diversified device structures can be provided on requirement.

公开(公告)号：US09911617B2

公开(公告)日：2018-03-06

申请号：US15299169

申请日：2016-10-20

Applicant: Institute of Microelectronics, Chinese Academy of Sciences

Inventor： Junjie Li ,  Junfeng Li ,  Qinghua Yang ,  Jinbiao Liu ,  Xiaobin He

IPC: B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3213

CPC classification number: H01L21/3065 ,  H01L21/3085 ,  H01L21/32136 ,  H01L21/32139

Abstract: The invention discloses a novel dry etching method, which comprises the following steps: forming a to-be-etched layer on a semiconductor substrate; forming a masking material on the to-be-etched layer; carrying out dry etching on the masking material and the to-be-etched layer; simultaneously carrying out lateral etching (parallel to the surface of the substrate) of a masking layer and longitudinal etching (vertical to the surface of the substrate) of the to-be-etched layer; and obtaining the inclination angle (the included angle between a slope surface and the surface of the substrate) of the corresponding etched slope surface by accurately controlling the speed ratio. The method can flexibly adjust the inclination angle of the etched slope surface within a large range (0-90 degrees), and especially has advantages in the field of the application with a small inclination angle (smaller than 20 degrees) of the etched slope surface in comparison with a conventional etching method.

公开(公告)号：US20250006822A1

公开(公告)日：2025-01-02

申请号：US18708028

申请日：2023-11-27

Applicant: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES

Inventor： Na Zhou ,  Junjie Li ,  Jianfeng Gao ,  Tao Yang ,  Junfeng Li ,  Jun Luo

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A method for manufacturing a gate-all-around TFET device. The method comprises: forming, on a substrate, a channel stack comprising channel layer(s) and sacrificial layer(s) that alternate with each other; forming, on the substrate, a dummy gate astride the channel stack; forming a first spacer at a surface of the dummy gate; etching the sacrificial layer(s) to form recesses on side surfaces of the channel stack; forming second spacers in the recesses, respectively; fabricating a source and a drain separately, where a region for fabricating the source is shielded by a dielectric material when fabricating the drain, and a region for fabricating the drain is shielded by another dielectric material when fabricating the source; etching the dummy gate and the sacrificial layer(s) to form a space for a surrounding gate; and fabricating a surrounding dielectric-metal gate in the space.