公开(公告)号：US20240005974A1

公开(公告)日：2024-01-04

申请号：US18247446

申请日：2021-01-04

Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES

Inventor： Guozhong XING ,  Huai LIN ,  Yu LIU ,  Kaiping ZHANG ,  Kangwei ZHANG ,  Hangbing LV ,  Changqing XIE ,  Qi LIU ,  Ling LI ,  Ming LIU

IPC: G11C11/16

CPC classification number: G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1673

Abstract: A self-reference storage structure includes: three transistors, including a first transistor T1, a second transistor T2, and a third transistor T3; and two magnetic tunnel junctions, including a first magnetic tunnel junction MTJ0 and a second magnetic tunnel junction MTJ1. The first magnetic tunnel junction MTJ0 is connected in series between the first transistor T1 and the second transistor T2, and the second magnetic tunnel junction MTJ1 is connected in series between the second transistor T2 and the third transistor T3. When the first transistor T1, the second transistor T2 and the third transistor T3 are turned on, one-bit binary information is written; and when data is stored, one-bit binary write can be implemented only by applying an unidirectional current pulse.

公开(公告)号：US20220310146A1

公开(公告)日：2022-09-29

申请号：US17594684

申请日：2020-08-07

Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES

Inventor： Guozhong XING ,  Huai LIN ,  Cheng LU ,  Qi LIU ,  Hangbing LV ,  Ling LI ,  Ming LIU

IPC: G11C11/16 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22

Abstract: The disclosure provides a spintronic device, a SOT-MRAM storage cell, a storage array and a in-memory computing circuit. The spintronic device includes a ferroelectric/ferromagnetic heterostructure, a magnetic tunnel junction, and a heavy metal layer between the ferroelectric/ferromagnetic heterostructure and the magnetic tunnel junction; the ferroelectric/ferromagnetic heterostructure includes a multiferroic material layer and a ferromagnetic layer arranged in a stacked manner, and the magnetic tunnel junction includes a free layer, an insulating layer and a reference layer arranged in a stacked manner, and the heavy metal layer is disposed between the ferromagnetic layer and the free layer. According to one or more embodiments of the disclosure, the spintronic device, the SOT-MRAM storage cell, the storage array and the in-memory computing circuit can realize deterministic magnetization inversion under the condition of no applied field assistance.

公开(公告)号：US20230124011A1

公开(公告)日：2023-04-20

申请号：US18061953

申请日：2022-12-05

Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES

Inventor： Guozhong XING ,  Huai LIN ,  Di WANG ,  Long LIU ,  Kaiping ZHANG ,  Guanya WANG ,  Yan WANG ,  Xiaoxin XU ,  Ming LIU

IPC: H04L9/32 ,  H10N50/10 ,  G11C11/16 ,  H10N50/85 ,  H01F10/32 ,  G11C11/14 ,  G06F7/58 ,  H10N50/80

Abstract: A reconfigurable PUF device based on fully electric field-controlled domain wall motion includes a voltage control layer, upper electrodes, a lower electrode, antiferromagnetic pinning layers, and a magnetic tunnel junction (MTJ). The MTJ includes, from bottom to top, a ferromagnetic reference layer, a potential barrier tunneling layer and a ferromagnetic free layer. In the device, an energy potential well is formed in a middle portion of the ferromagnetic free layer by applying a voltage to the voltage control layer to control magnetic anisotropy, and a current is fed into either of the upper electrodes to drive generation of the magnetic domain walls and pin the magnetic domain walls to the potential well. After the voltage is removed, the potential well is lowered so that the magnetic domain walls are in a metastable state, thereby either a high resistance state or a low resistance state is randomly obtained.

公开(公告)号：US20230046423A1

公开(公告)日：2023-02-16

申请号：US17821783

申请日：2022-08-23

Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES

Inventor： Guozhong XING ,  Long LIU ,  Di WANG ,  Huai LIN ,  Ming LIU

IPC: G11C11/16 ,  G11C11/54

Abstract: A magnetoresistive memory cell includes a first magnetic tunnel junction, a second magnetic tunnel junction and a metal layer. The first magnetic tunnel junction and the second magnetic tunnel junction each are disposed on the metal layer; the metal layer is configured to pass write current, a projection line of an easy axis of the first magnetic tunnel junction on a plane where the metal layer is located forms a first angle against a direction of the write current, and a projection line of an easy axis of the second magnetic tunnel junction on the plane where the metal layer is located forms a second angle against a direction opposite to the direction of the write current; the first angle and the second angle are all less than 90°; the first magnetic tunnel junction and the second magnetic tunnel junction are configured to pass read current.