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公开(公告)号:US20240005974A1
公开(公告)日:2024-01-04
申请号:US18247446
申请日:2021-01-04
Inventor: Guozhong XING , Huai LIN , Yu LIU , Kaiping ZHANG , Kangwei ZHANG , Hangbing LV , Changqing XIE , Qi LIU , Ling LI , Ming LIU
IPC: G11C11/16
CPC classification number: G11C11/161 , G11C11/1659 , G11C11/1675 , G11C11/1673
Abstract: A self-reference storage structure includes: three transistors, including a first transistor T1, a second transistor T2, and a third transistor T3; and two magnetic tunnel junctions, including a first magnetic tunnel junction MTJ0 and a second magnetic tunnel junction MTJ1. The first magnetic tunnel junction MTJ0 is connected in series between the first transistor T1 and the second transistor T2, and the second magnetic tunnel junction MTJ1 is connected in series between the second transistor T2 and the third transistor T3. When the first transistor T1, the second transistor T2 and the third transistor T3 are turned on, one-bit binary information is written; and when data is stored, one-bit binary write can be implemented only by applying an unidirectional current pulse.
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公开(公告)号:US20220310146A1
公开(公告)日:2022-09-29
申请号:US17594684
申请日:2020-08-07
Inventor: Guozhong XING , Huai LIN , Cheng LU , Qi LIU , Hangbing LV , Ling LI , Ming LIU
Abstract: The disclosure provides a spintronic device, a SOT-MRAM storage cell, a storage array and a in-memory computing circuit. The spintronic device includes a ferroelectric/ferromagnetic heterostructure, a magnetic tunnel junction, and a heavy metal layer between the ferroelectric/ferromagnetic heterostructure and the magnetic tunnel junction; the ferroelectric/ferromagnetic heterostructure includes a multiferroic material layer and a ferromagnetic layer arranged in a stacked manner, and the magnetic tunnel junction includes a free layer, an insulating layer and a reference layer arranged in a stacked manner, and the heavy metal layer is disposed between the ferromagnetic layer and the free layer. According to one or more embodiments of the disclosure, the spintronic device, the SOT-MRAM storage cell, the storage array and the in-memory computing circuit can realize deterministic magnetization inversion under the condition of no applied field assistance.
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