公开(公告)号：US20220310146A1

公开(公告)日：2022-09-29

申请号：US17594684

申请日：2020-08-07

Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES

Inventor： Guozhong XING ,  Huai LIN ,  Cheng LU ,  Qi LIU ,  Hangbing LV ,  Ling LI ,  Ming LIU

IPC: G11C11/16 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22

Abstract: The disclosure provides a spintronic device, a SOT-MRAM storage cell, a storage array and a in-memory computing circuit. The spintronic device includes a ferroelectric/ferromagnetic heterostructure, a magnetic tunnel junction, and a heavy metal layer between the ferroelectric/ferromagnetic heterostructure and the magnetic tunnel junction; the ferroelectric/ferromagnetic heterostructure includes a multiferroic material layer and a ferromagnetic layer arranged in a stacked manner, and the magnetic tunnel junction includes a free layer, an insulating layer and a reference layer arranged in a stacked manner, and the heavy metal layer is disposed between the ferromagnetic layer and the free layer. According to one or more embodiments of the disclosure, the spintronic device, the SOT-MRAM storage cell, the storage array and the in-memory computing circuit can realize deterministic magnetization inversion under the condition of no applied field assistance.

公开(公告)号：US20220261621A1

公开(公告)日：2022-08-18

申请号：US17597720

申请日：2019-11-13

Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES

Inventor： Qi LIU ,  Zuheng WU ,  Tuo SHI ,  Ming LIU ,  Hangbing LV ,  Xumeng ZHANG ,  Wei WANG

IPC: G06N3/063 ,  H01L27/24 ,  H01L45/00

Abstract: Disclosed are an artificial sensory nervous circuit and a manufacturing method thereof. The artificial sensory nervous circuit includes a sensor (S), a first memristor (RS), and a neuron circuit, where the first memristor (RS) has a unidirectional resistance characteristic. The sensor (S) is configured to sensing an external signal and generating an excitation signal according to the external signal. The first memristor (RS) is configured to generating a response signal according to the excitation signal. The neuron circuit is configured to perform charging and discharging according to the response signal so as to output a pulse signal. With the artificial sensory nervous circuit and the manufacturing method thereof, sensitivity and habituation characteristics of biological perception are realized by using a simple circuit.

公开(公告)号：US20220253684A1

公开(公告)日：2022-08-11

申请号：US17597798

申请日：2019-11-29

Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES

Inventor： Qi LIU ,  Xumeng ZHANG ,  Ming LIU ,  Hangbing LV ,  Zuheng WU

IPC: G06N3/063 ,  H01L27/20

Abstract: Disclosed is an afferent neuron circuit, which includes: a resistance Rc and a volatile threshold switching device TS, wherein the volatile threshold switching device TS is provided with a parasitic capacitor Cparasitic; a first end of the resistance Rc serves as a signal input terminal, and a second end of the resistance Rc serves as a signal output terminal; and a first end of the volatile threshold switching device TS is connected to the signal output terminal, and a second end of the volatile threshold switching device TS is grounded. The afferent neuron circuit provided in the content of the present disclosure has a simple structure and good scalability and is suitable for large-scale integration.

公开(公告)号：US20240005974A1

公开(公告)日：2024-01-04

申请号：US18247446

申请日：2021-01-04

Applicant: INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES

Inventor： Guozhong XING ,  Huai LIN ,  Yu LIU ,  Kaiping ZHANG ,  Kangwei ZHANG ,  Hangbing LV ,  Changqing XIE ,  Qi LIU ,  Ling LI ,  Ming LIU

IPC: G11C11/16

CPC classification number: G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1673

Abstract: A self-reference storage structure includes: three transistors, including a first transistor T1, a second transistor T2, and a third transistor T3; and two magnetic tunnel junctions, including a first magnetic tunnel junction MTJ0 and a second magnetic tunnel junction MTJ1. The first magnetic tunnel junction MTJ0 is connected in series between the first transistor T1 and the second transistor T2, and the second magnetic tunnel junction MTJ1 is connected in series between the second transistor T2 and the third transistor T3. When the first transistor T1, the second transistor T2 and the third transistor T3 are turned on, one-bit binary information is written; and when data is stored, one-bit binary write can be implemented only by applying an unidirectional current pulse.