公开(公告)号：EP3234767A4

公开(公告)日：2018-07-18

申请号：EP15870563

申请日：2015-11-16

Applicant: INTEL CORP

Inventor： COLLINS JAMISON D ,  IYER JAYESH ,  WINKEL SEBASTIAN ,  XEKALAKIS POLYCHRONIS ,  CHEN HOWARD H ,  BRAUCH RUPERT

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30134 ,  G06F8/41 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/384 ,  G06F9/3859 ,  G06F9/3863

Abstract: Embodiments of a method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions. In one embodiment the apparatus is an out of order hardware/software co-designed processor including instructions to explicitly manage the predicate register stack to maintain stack consistency across branches of executing that push a variable number of predicate values onto the predicate stack. In one embodiment the stack-based predicate register implementation enables early branch calculation and early branch misprediction recovery via early renaming of predicate registers.