公开(公告)号：WO2012087561A3

公开(公告)日：2012-08-16

申请号：PCT/US2011063466

申请日：2011-12-06

Applicant: INTEL CORP ,  SAGER DAVID J ,  SASANKA RUCHIRA ,  GABOR RON ,  RAIKIN SHLOMO ,  NUZMAN JOSEPH ,  PELED LEEOR ,  DOMER JASON A ,  KIM HO-SEOP ,  WU YOUFENG ,  YAMADA KOICHI ,  NGAI TIN-FOOK ,  CHEN HOWARD H ,  BOBBA JAYARAM ,  COOK JEFFREY J ,  SHAIKH OSMAR M ,  SRINIVAS SURESH

Inventor： SAGER DAVID J ,  SASANKA RUCHIRA ,  GABOR RON ,  RAIKIN SHLOMO ,  NUZMAN JOSEPH ,  PELED LEEOR ,  DOMER JASON A ,  KIM HO-SEOP ,  WU YOUFENG ,  YAMADA KOICHI ,  NGAI TIN-FOOK ,  CHEN HOWARD H ,  BOBBA JAYARAM ,  COOK JEFFREY J ,  SHAIKH OSMAR M ,  SRINIVAS SURESH

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F8/4442 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/54 ,  G06F11/3612 ,  G06F11/3636 ,  G06F11/3648 ,  G06F2213/0038

Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

Abstract translation: 描述了用于将程序自动分解成多个并行线程的硬件和软件系统的系统，设备和方法。 在一些实施例中，系统和设备执行原始代码分解和/或生成的线程执行的方法。

公开(公告)号：DE112011104596T5

公开(公告)日：2014-01-16

申请号：DE112011104596

申请日：2011-12-06

Applicant: INTEL CORP

Inventor： SAGER DAVID J ,  RAIKIN SHLOMO ,  DOMER JASON A ,  SASANKA RUCHIRA ,  GABOR RON ,  NUZMAN JOSEPH ,  PELED LEEOR ,  KIM HO-SEOP ,  WU YOUFENG ,  YAMADA KOICHI ,  NGAI TIN-FOOK ,  CHEN HOWARD H ,  BOBBA JAYARAM ,  COOK JEFFREY J ,  SHAIKH OSMAR M ,  SRINIVAS SURESH

IPC: G06F9/30 ,  G06F9/38

Abstract: Systeme, Vorrichtungen und Verfahren für ein Hardware- und Softwaresystem zum automatischen Zerlegen eines Programms in mehrere parallele Threads werden beschrieben. In einigen Ausführungsformen führen die Systeme und Vorrichtungen ein Verfahren zum Zerlegen eines ursprünglichen Codes und/oder einer generierten Thread-Ausführung aus.

公开(公告)号：GB2499762A

公开(公告)日：2013-08-28

申请号：GB201310833

申请日：2011-12-06

Applicant: INTEL CORP

Inventor： SAGER DAVID J ,  SASANKA RUCHIRA ,  GABOR RON ,  RAIKIN SHLOMO ,  NUZMAN JOSEPH ,  PELED LEEOR ,  DOMER JASON A ,  KIM HO-SEOP ,  WU YOUFENG ,  YAMADA KOICHI ,  NGAI TIN-FOOK ,  CHEN HOWARD H ,  BOBBA JAYARAM ,  COOK JEFFREY J ,  SHAIKH OSMAR M ,  SRINIVAS SURESH

IPC: G06F9/38 ,  G06F9/54 ,  G06F11/36

Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.

公开(公告)号：EP3234767A4

公开(公告)日：2018-07-18

申请号：EP15870563

申请日：2015-11-16

Applicant: INTEL CORP

Inventor： COLLINS JAMISON D ,  IYER JAYESH ,  WINKEL SEBASTIAN ,  XEKALAKIS POLYCHRONIS ,  CHEN HOWARD H ,  BRAUCH RUPERT

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30134 ,  G06F8/41 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/384 ,  G06F9/3859 ,  G06F9/3863

Abstract: Embodiments of a method and apparatus for implementing and maintaining a stack of predicate values with stack synchronization instructions. In one embodiment the apparatus is an out of order hardware/software co-designed processor including instructions to explicitly manage the predicate register stack to maintain stack consistency across branches of executing that push a variable number of predicate values onto the predicate stack. In one embodiment the stack-based predicate register implementation enables early branch calculation and early branch misprediction recovery via early renaming of predicate registers.