TWO-LEVEL SYSTEM MAIN MEMORY
    2.
    发明申请
    TWO-LEVEL SYSTEM MAIN MEMORY 审中-公开
    两级系统主要内存

    公开(公告)号:WO2012087471A3

    公开(公告)日:2013-01-10

    申请号:PCT/US2011061466

    申请日:2011-11-18

    Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes "near memory" comprising memory made of volatile memory, and "far memory" comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as "main memory" to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

    Abstract translation: 本发明的实施例描述了包括两级存储器的系统主存储器,其包括系统盘级存储器的缓存子集。 该主存储器包括包含由易失性存储器构成的存储器的“近存储器”和包括比近存储器更大和更慢的易失性或非易失性存储器存储器的“远存储器”。 远端存储器被呈现为主机OS的“主存储器”,而近端存储器是对OS是透明的远存储器的高速缓存,因此与OS显示与现有技术的主存储器解决方案相同。 两级存储器的管理可以通过经由主机CPU执行的逻辑和模块的组合来完成。 近端存储器可以通过高带宽,低延迟的方式耦合到主机系统CPU,用于高效处理。 远端存储器可以通过低带宽,高延迟手段耦合到CPU。

    TWO-LEVEL SYSTEM MAIN MEMORY
    4.
    发明公开
    TWO-LEVEL SYSTEM MAIN MEMORY 审中-公开
    HAUPTSPEICHERFÜREIN ZWEISTUFIGES系统

    公开(公告)号:EP2656225A4

    公开(公告)日:2015-01-21

    申请号:EP11851888

    申请日:2011-11-18

    Applicant: INTEL CORP

    Abstract: Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes "near memory" comprising memory made of volatile memory, and "far memory" comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as "main memory" to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.

    Abstract translation: 本发明的实施例描述了包括两级存储器的系统主存储器,其包括系统盘级存储器的缓存子集。 该主存储器包括包含由易失性存储器构成的存储器的“近存储器”和包括比近存储器更大和更慢的易失性或非易失性存储器存储器的“远存储器”。 远端存储器被呈现为主机OS的“主存储器”,而近端存储器是对OS是透明的远存储器的高速缓存,因此与OS显示与现有技术的主存储器解决方案相同。 两级存储器的管理可以通过经由主机CPU执行的逻辑和模块的组合来完成。 近端存储器可以通过高带宽,低延迟的方式耦合到主机系统CPU,用于高效处理。 远端存储器可以通过低带宽,高延迟手段耦合到CPU。

    A METHOD, APPARATUS, AND SYSTEM FOR MANAGEABILITY AND SECURE ROUTING AND ENDPOINT ACCESS
    6.
    发明公开
    A METHOD, APPARATUS, AND SYSTEM FOR MANAGEABILITY AND SECURE ROUTING AND ENDPOINT ACCESS 审中-公开
    VERFAHREN,VORRICHTUNG UND系统FÜRVERWALTBARKEIT,SICHERES ROUTING UND ENDPUNKTZUGANG

    公开(公告)号:EP2606606A4

    公开(公告)日:2017-09-06

    申请号:EP11818524

    申请日:2011-07-22

    Applicant: INTEL CORP

    Abstract: A solution is presented to securing endpoints without the need for a separate bus or communication path. The solution allows for controlling access to endpoints by utilizing a management protocol by overlapping with existing interconnect communication paths in a packet format and utilizing a PCI address BDF (Bus number, Device number, and Function number) for verification.

    Abstract translation: 提出了一种解决方案来保护端点,而不需要单独的总线或通信路径。 该解决方案允许通过利用管理协议通过与分组格式中的现有互连通信路径重叠并利用PCI地址BDF(总线号,设备号和功能号)进行验证来控制对端点的访问。

Patent Agency Ranking