Abstract:
A solution is presented to securing endpoints without the need for a separate bus or communication path. The solution allows for controlling access to endpoints by utilizing a management protocol by overlapping with existing interconnect communication paths in a packet format and utilizing a PCI address BDF (Bus number, Device number, and Function number) for verification.
Abstract:
Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes "near memory" comprising memory made of volatile memory, and "far memory" comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as "main memory" to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
Abstract:
Ausführungsformen von Systemen, Geräten und Verfahren stellen Benutzern, zum Beispiel Computerentwicklern und Cloud-Service-Anbietern (CSPs), verbesserte Function-as-a-Service (FaaS) bereit. Ein Rechensystem, das dazu konfiguriert ist, solche verbesserte Function-as-a-Service bereitzustellen, beinhaltet ein oder mehrere Steuerarchitektursubsysteme, Software und Orchestrierungssubsysteme, Netzwerk- und Lagerungssubsysteme und Sicherheitssubsysteme. Das Rechensystem führt Funktionen als Reaktion auf Ereignisse aus, die von den Benutzern in einer Ausführungsumgebung ausgelöst werden, die von den Architektursubsystemen bereitgestellt wird, die eine Abstraktion des Ausführungsmanagements darstellen und die Benutzer von der Bürde des Managements der Ausführung abschirmen. Die Software- und Orchestrierungssubsysteme ordnen Rechenressourcen für die Funktionsausführung zu, indem sie intelligent Container für einen Funktionscode mit verringerter Instanziierungslatenz und gesteigerter Ausführungsskalierbarkeit hochlaufen und herunterlaufen lassen, während sie gesicherte Ausführung beibehalten. Außerdem ermöglicht es das Rechensystem Kunden, mit einer feinen Abrechnung bis hinunter zu Millisekunden Inkrementen, nur zu bezahlen, wenn ihr Code ausgeführt wird.
Abstract:
Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes "near memory" comprising memory made of volatile memory, and "far memory" comprising volatile or nonvolatile memory storage that is larger and slower than the near memory. The far memory is presented as "main memory" to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
Abstract:
In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for presentation of direct accessed storage under a logical drive model; for implementing a distributed architecture for cooperative NVM Data protection; data mirroring for consistent SSD latency; for boosting a controller's performance and RAS with DIF support via concurrent RAID processing; for implementing arbitration and resource schemes of a doorbell mechanism, including doorbell arbitration for fairness and prevention of attack congestion; and for implementing multiple interrupt generation using a messaging unit and NTB in a controller through use of an interrupt coalescing scheme.
Abstract:
A solution is presented to securing endpoints without the need for a separate bus or communication path. The solution allows for controlling access to endpoints by utilizing a management protocol by overlapping with existing interconnect communication paths in a packet format and utilizing a PCI address BDF (Bus number, Device number, and Function number) for verification.