公开(公告)号：WO9711418A3

公开(公告)日：1997-05-09

申请号：PCT/US9611716

申请日：1996-07-15

Applicant: INTEL CORP ,  AJANOVIC JASMIN ,  MURDOCH ROBERT N ,  DOBBINS TIMOTHY M ,  SREENIVAS ADITYA ,  SAILER STUART E ,  RABE JEFFREY L

Inventor： AJANOVIC JASMIN ,  MURDOCH ROBERT N ,  DOBBINS TIMOTHY M ,  SREENIVAS ADITYA ,  SAILER STUART E ,  RABE JEFFREY L

IPC: G06F13/362 ,  G06F

CPC classification number: G06F13/362

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer. The transaction processor unit defers the transactions issued on the bus when the transaction processor receives the indication signal indicating that a pending transaction is waiting to be issued on the bus, when the encoded signals from the transaction issued on the bus indicate that the transaction issued on the bus is a candidate for deferral, and when the CPU latency timer outputs the expiration signal.

公开(公告)号：HK1016300A1

公开(公告)日：1999-10-29

申请号：HK99101367

申请日：1999-04-07

Applicant: INTEL CORP

Inventor： AJANOVIC JASMIN ,  MURDOCH ROBERT N ,  DOBBINS TIMOTHY M ,  SREENIVAS ADITYA ,  SAILER STUART E ,  RABE JEFFREY L

IPC: G06F13/362 ,  G06F

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer. The transaction processor unit defers the transactions issued on the bus when the transaction processor receives the indication signal indicating that a pending transaction is waiting to be issued on the bus, when the encoded signals from the transaction issued on the bus indicate that the transaction issued on the bus is a candidate for deferral, and when the CPU latency timer outputs the expiration signal.

公开(公告)号：GB2287862A

公开(公告)日：1995-09-27

申请号：GB9501874

申请日：1995-01-31

Applicant: INTEL CORP

Inventor： DOBBINS TIMOTHY M ,  BOGIN ZOHAR

IPC: G06F1/22 ,  G06F13/00 ,  G06F13/364 ,  G06F13/36 ,  H04L12/403 ,  G06F13/362

Abstract: Semiconductor components 103 and 104 transmit to each other on link 106 and line 169 a plurality of different signal types (addresses, command, status, data). Line 169 is a shared line for transmission also of signals (e.g. address) between components 103 and 101. The components 101, 103 and 104 are microprocessors, microcontrollers, bus controllers, memory controllers, etc. Transmissions of different types of signals on the same line or link leads to sharing pins and consequent size reductions of components 101, 103 and 104. An arbiter (630) Fig. 6 (not shown) arbitrates access to the shared line 169, receiving request signals and sending grant signals.

公开(公告)号：FR2717645A1

公开(公告)日：1995-09-22

申请号：FR9503048

申请日：1995-03-16

Applicant: INTEL CORP

Inventor： DOBBINS TIMOTHY M ,  ZOHAR BOGIN

IPC: G06F1/22 ,  G06F13/00 ,  G06F13/36 ,  G06F13/364 ,  H04L12/40

Abstract: A semiconductor component is which is capable of controlling transmission of information between a plurality of semiconductor components in a computer system. The semiconductor component comprises of a first signal generator capable of sending a signal of a first type over a shared line and a second signal generator capable of sending a signal of a second type over the line. It also comprises of a first logic device capable of controlling the first signal generator and a second logic device capable of controlling the second signal generator.

公开(公告)号：FR2717645B1

公开(公告)日：2004-08-20

申请号：FR9503048

申请日：1995-03-16

Applicant: INTEL CORP

Inventor： DOBBINS TIMOTHY M ,  BOGIN ZOHAR

IPC: G06F1/22 ,  G06F13/36 ,  G06F13/00 ,  G06F13/364 ,  H04L12/40

Abstract: A semiconductor component is which is capable of controlling transmission of information between a plurality of semiconductor components in a computer system. The semiconductor component comprises of a first signal generator capable of sending a signal of a first type over a shared line and a second signal generator capable of sending a signal of a second type over the line. It also comprises of a first logic device capable of controlling the first signal generator and a second logic device capable of controlling the second signal generator.

公开(公告)号：DE19580195T1

公开(公告)日：1997-01-16

申请号：DE19580195

申请日：1995-03-17

Applicant: INTEL CORP

Inventor： DOBBINS TIMOTHY M ,  BOGIN ZOHAR

IPC: G06F13/36 ,  G06F1/22 ,  G06F13/00 ,  G06F13/364

Abstract: A semiconductor component is which is capable of controlling transmission of information between a plurality of semiconductor components in a computer system. The semiconductor component comprises of a first signal generator capable of sending a signal of a first type over a shared line and a second signal generator capable of sending a signal of a second type over the line. It also comprises of a first logic device capable of controlling the first signal generator and a second logic device capable of controlling the second signal generator.

公开(公告)号：DE19580195C2

公开(公告)日：2003-07-03

申请号：DE19580195

申请日：1995-03-17

Applicant: INTEL CORP

Inventor： DOBBINS TIMOTHY M ,  BOGIN ZOHAR

IPC: G06F13/36 ,  G06F1/22 ,  G06F13/00 ,  G06F13/364

Abstract: A semiconductor component is which is capable of controlling transmission of information between a plurality of semiconductor components in a computer system. The semiconductor component comprises of a first signal generator capable of sending a signal of a first type over a shared line and a second signal generator capable of sending a signal of a second type over the line. It also comprises of a first logic device capable of controlling the first signal generator and a second logic device capable of controlling the second signal generator.

公开(公告)号：AU6493796A

公开(公告)日：1997-04-09

申请号：AU6493796

申请日：1996-07-15

Applicant: INTEL CORP

Inventor： AJANOVIC JASMIN ,  MURDOCH ROBERT N ,  DOBBINS TIMOTHY M ,  SREENIVAS ADITYA ,  SAILER STUART E ,  RABE JEFFREY L

IPC: G06F13/362 ,  G06F17/00 ,  G06F19/00

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer. The transaction processor unit defers the transactions issued on the bus when the transaction processor receives the indication signal indicating that a pending transaction is waiting to be issued on the bus, when the encoded signals from the transaction issued on the bus indicate that the transaction issued on the bus is a candidate for deferral, and when the CPU latency timer outputs the expiration signal.

公开(公告)号：EP0870240A4

公开(公告)日：2001-10-24

申请号：EP96924504

申请日：1996-07-15

Applicant: INTEL CORP

Inventor： AJANOVIC JASMIN ,  MURDOCH ROBERT N ,  DOBBINS TIMOTHY M ,  SREENIVAS ADITYA ,  SAILER STUART E ,  RABE JEFFREY L

IPC: G06F13/362 ,  G06F13/00 ,  G06F13/36

CPC classification number: G06F13/362

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer. The transaction processor unit defers the transactions issued on the bus when the transaction processor receives the indication signal indicating that a pending transaction is waiting to be issued on the bus, when the encoded signals from the transaction issued on the bus indicate that the transaction issued on the bus is a candidate for deferral, and when the CPU latency timer outputs the expiration signal.

公开(公告)号：MY119493A

公开(公告)日：2005-06-30

申请号：MYPI9602723

申请日：1996-07-03

Applicant: INTEL CORP

Inventor： SREENIVAS ADITYA ,  AJANOVIC JASMIN ,  RABE JEFFREY L ,  MURDOCH ROBERT N ,  SAILER STUART E ,  DOBBINS TIMOTHY M

IPC: G06F13/362

Abstract: A METHOD AND APPARATUS FOR REGULATING THE DEFERRAL OF A TRANSACTION ISSUED ON A BUS (120) BY A PROCESSOR IN A COMPUTER SYSTEM IS DISCLOSED. A BUS TRANSACTION RECORDER (221) COUPLED TO THE BUS PROCESSES ENCODED SIGNALS FROM THE TRANSACTION ISSUED ON THE BUS. A LINE COUPLED TO THE BUS SENDS AN INDICATION SIGNAL WHEN A PENDING TRANSACTION REQUEST IS ISSUED ON THE BUS. A CPU LATENCY TIMER TIMES THE CURRENT TRANSACTION ON THE BUS WHEN A NEW PENDING TRANSACTION IS WAITING ON THE BUS (120). THE CPU LATENCY TIMER OUTPUTS AN EXPIRATION SIGNAL WHEN THE TRANSACTION TAKES MORE THAN A PREDETERMINED AMOUNT OF TIME TO COMPLETE. A TRANSACTION PROCESSOR UNIT (222) IS COUPLED TO THE BUS TRANSACTION RECORDER (221), THE LINE, AND THE CPU LATENCY TIMER. THE TRANSACTION PROCESSOR UNIT (222) DEFERS THE TRANSACTIONS ISSUED ON THE BUS WHEN THE TRANSACTION PROCESSOR RECEIVES THE INDICATION SIGNAL INDICATING THAT A PENDING TRANSACTION IS WAITING TO BE ISSUED ON THE BUS (120), WHEN THE ENCODED SIGNALS FROM THE TRANSACTION ISSUED ON THE BUS (120) INDICATE THAT THE TRANSACTION ISSUED ON THE BUS (120) IS A CANDIDATE FOR DEFERRAL, AND WHEN THE CPU LATENCY TIMER OUTPUTS THE EXPIRATION SIGNAL. (FIG.1)