公开(公告)号：WO0042594A9

公开(公告)日：2002-03-28

申请号：PCT/US0000776

申请日：2000-01-12

Applicant: INTEL CORP ,  DOYLE PETER ,  SREENIVAS ADITYA

Inventor： DOYLE PETER ,  SREENIVAS ADITYA

IPC: G06T1/60 ,  G06F12/00 ,  G06F12/02 ,  G06T1/20 ,  G09G5/36 ,  G09G5/39 ,  G09G5/393 ,  G09G1/16

CPC classification number: G09G5/363 ,  G09G5/393 ,  G09G2360/122

Abstract: A method and apparatus for implementing a dynamic display memory is provided. A memory control hub suitable for interposition between a central processor and a memory includes a graphics memory control component. The graphics memory control component determines whether operands accessed by the central processor are graphics operands. If so, the graphics memory control component transforms the virtual address supplied by the central processor to a system address suitable for use in locating the graphics operand in the memory. In one embodiment, the graphics control component maintains a graphics translation table in the memory and utilizes the graphics translation table in transforming virtual addresses to system addresses. Furthermore, in one embodiment, the graphics control component reorders the addresses of the graphics operands to optimize for performance memory accesses by a graphics device.

Abstract translation: 提供了一种用于实现动态显示存储器的方法和装置。 适于中央处理器和存储器之间插入的存储器控​​制中心包括图形存储器控制部件。 图形存储器控制组件确定中央处理器访问的操作数是否是图形操作数。 如果是这样，则图形存储器控制部件将由中央处理器提供的虚拟地址转换成适合于将图形操作数定位在存储器中的系统地址。 在一个实施例中，图形控制组件在存储器中维护图形转换表，并利用图形转换表将虚拟地址转换成系统地址。 此外，在一个实施例中，图形控制部件重新排列图形操作数的地址以优化图形设备的性能存储器访问。

公开(公告)号：WO0041083A3

公开(公告)日：2002-05-16

申请号：PCT/US9930719

申请日：1999-12-21

Applicant: INTEL CORP ,  CLOHSET STEVE J ,  DIEP TRUNG A ,  GANDHI WISHWESH ,  PIAZZA THOMAS A ,  SREENIVAS ADITYA ,  TRIEU TUONG P

Inventor： CLOHSET STEVE J ,  DIEP TRUNG A ,  GANDHI WISHWESH ,  PIAZZA THOMAS A ,  SREENIVAS ADITYA ,  TRIEU TUONG P

IPC: G06F12/00 ,  G06F12/02 ,  G06F13/18 ,  G06F13/362

CPC classification number: G06F13/18

Abstract: According to one embodiment, a computer system is disclosed that includes a memory and a memory controller coupled to the memory. The memory controller includes an arbitration unit that may be programmed to operate according to a first arbitration mode or a second arbitration mode. The computer system also includes a first device and a second device coupled to the arbitration unit. According to a further embodiment, the first device is assigned a higher priority classification than the second device for accessing the memory while the arbitration unit is operating according to the first arbitration mode. In addition, the first device and the second device are assigned equal priority classifications for accessing the memory while the arbitration unit is operating according to the second arbitration mode.

Abstract translation: 根据一个实施例，公开了一种包括存储器和耦合到存储器的存储器控​​制器的计算机系统。 存储器控制器包括可被编程为根据第一仲裁模式或第二仲裁模式进行操作的仲裁单元。 计算机系统还包括耦合到仲裁单元的第一设备和第二设备。 根据另一实施例，当仲裁单元根据第一仲裁模式操作时，第一设备被分配比用于访问存储器的第二设备更高的优先级分类。 此外，当仲裁单元根据第二仲裁模式操作时，第一设备和第二设备被分配用于访问存储器的相同的优先级分类。

公开(公告)号：WO03003206A2

公开(公告)日：2003-01-09

申请号：PCT/US0220682

申请日：2002-06-28

Applicant: INTEL CORP

Inventor： DOYLE PETER ,  SREENIVAS ADITYA

IPC: G06T1/60 ,  G06F9/46 ,  G06T11/00 ,  G06F9/48

CPC classification number: G06F9/463

Abstract: A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A graphics context manager stores in a first memory area and restores from the first memory area information describing a first rendering context associated with a first independent image. The graphics context manager stores in a second memory area and restores from the second memory area information describing a second rendering context associated with a second independent image.

Abstract translation: 一种同时呈现独立图像以在一个或多个显示设备上显示的方法，设备和系统。 在一个实施例中，图形渲染引擎同时渲染独立图像以在多个显示设备上显示。 图形上下文管理器存储在第一存储器区域中并且从第一存储器区域恢复描述与第一独立图像相关联的第一渲染上下文的信息。 图形上下文管理器存储在第二存储区域中，并且从第二存储区域恢复描述与第二独立图像相关联的第二渲染上下文的信息。

公开(公告)号：WO9711418A3

公开(公告)日：1997-05-09

申请号：PCT/US9611716

申请日：1996-07-15

Applicant: INTEL CORP ,  AJANOVIC JASMIN ,  MURDOCH ROBERT N ,  DOBBINS TIMOTHY M ,  SREENIVAS ADITYA ,  SAILER STUART E ,  RABE JEFFREY L

Inventor： AJANOVIC JASMIN ,  MURDOCH ROBERT N ,  DOBBINS TIMOTHY M ,  SREENIVAS ADITYA ,  SAILER STUART E ,  RABE JEFFREY L

IPC: G06F13/362 ,  G06F

CPC classification number: G06F13/362

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer. The transaction processor unit defers the transactions issued on the bus when the transaction processor receives the indication signal indicating that a pending transaction is waiting to be issued on the bus, when the encoded signals from the transaction issued on the bus indicate that the transaction issued on the bus is a candidate for deferral, and when the CPU latency timer outputs the expiration signal.

公开(公告)号：DE69924039D1

公开(公告)日：2005-04-07

申请号：DE69924039

申请日：1999-12-21

Applicant: INTEL CORP

Inventor： CLOHSET J ,  DIEP A ,  GANDHI WISHWESH ,  PIAZZA A ,  SREENIVAS ADITYA ,  TRIEU P

IPC: G06F12/00 ,  G06F12/02 ,  G06F13/18 ,  G06F13/362

Abstract: According to one embodiment, a computer system is disclosed that includes a memory and a memory controller coupled to the memory. The memory controller includes an arbitration unit that may be programmed to operate according to a first arbitration mode or a second arbitration mode. The computer system also includes a first device and a second device coupled to the arbitration unit. According to a further embodiment, the first device is assigned a higher priority classification than the second device for accessing the memory while the arbitration unit is operating according to the first arbitration mode. In addition, the first device and the second device are assigned equal priority classifications for accessing the memory while the arbitration unit is operating according to the second arbitration mode.

公开(公告)号：DE69625826T2

公开(公告)日：2003-11-06

申请号：DE69625826

申请日：1996-07-15

Applicant: INTEL CORP

Inventor： AJANOVIC JASMIN ,  MURDOCH N ,  DOBBINS M ,  SREENIVAS ADITYA ,  SAILER E ,  RABE L

IPC: G06F13/362 ,  G06F13/00 ,  G06F13/36

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer. The transaction processor unit defers the transactions issued on the bus when the transaction processor receives the indication signal indicating that a pending transaction is waiting to be issued on the bus, when the encoded signals from the transaction issued on the bus indicate that the transaction issued on the bus is a candidate for deferral, and when the CPU latency timer outputs the expiration signal.

公开(公告)号：AU2002322363A1

公开(公告)日：2003-03-03

申请号：AU2002322363

申请日：2002-06-28

Applicant: INTEL CORP

Inventor： DOYLE PETER ,  SREENIVAS ADITYA

IPC: G06F3/14 ,  G06T15/00 ,  G06T17/00 ,  G06T1/20

Abstract: A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A time allocator arbitrates the concurrent use of the graphics-rendering engine between each independent image being rendered.

公开(公告)号：MY119493A

公开(公告)日：2005-06-30

申请号：MYPI9602723

申请日：1996-07-03

Applicant: INTEL CORP

Inventor： SREENIVAS ADITYA ,  AJANOVIC JASMIN ,  RABE JEFFREY L ,  MURDOCH ROBERT N ,  SAILER STUART E ,  DOBBINS TIMOTHY M

IPC: G06F13/362

Abstract: A METHOD AND APPARATUS FOR REGULATING THE DEFERRAL OF A TRANSACTION ISSUED ON A BUS (120) BY A PROCESSOR IN A COMPUTER SYSTEM IS DISCLOSED. A BUS TRANSACTION RECORDER (221) COUPLED TO THE BUS PROCESSES ENCODED SIGNALS FROM THE TRANSACTION ISSUED ON THE BUS. A LINE COUPLED TO THE BUS SENDS AN INDICATION SIGNAL WHEN A PENDING TRANSACTION REQUEST IS ISSUED ON THE BUS. A CPU LATENCY TIMER TIMES THE CURRENT TRANSACTION ON THE BUS WHEN A NEW PENDING TRANSACTION IS WAITING ON THE BUS (120). THE CPU LATENCY TIMER OUTPUTS AN EXPIRATION SIGNAL WHEN THE TRANSACTION TAKES MORE THAN A PREDETERMINED AMOUNT OF TIME TO COMPLETE. A TRANSACTION PROCESSOR UNIT (222) IS COUPLED TO THE BUS TRANSACTION RECORDER (221), THE LINE, AND THE CPU LATENCY TIMER. THE TRANSACTION PROCESSOR UNIT (222) DEFERS THE TRANSACTIONS ISSUED ON THE BUS WHEN THE TRANSACTION PROCESSOR RECEIVES THE INDICATION SIGNAL INDICATING THAT A PENDING TRANSACTION IS WAITING TO BE ISSUED ON THE BUS (120), WHEN THE ENCODED SIGNALS FROM THE TRANSACTION ISSUED ON THE BUS (120) INDICATE THAT THE TRANSACTION ISSUED ON THE BUS (120) IS A CANDIDATE FOR DEFERRAL, AND WHEN THE CPU LATENCY TIMER OUTPUTS THE EXPIRATION SIGNAL. (FIG.1)

公开(公告)号：AU2002360575A1

公开(公告)日：2003-07-24

申请号：AU2002360575

申请日：2002-12-11

Applicant: INTEL CORP

Inventor： SREENIVAS ADITYA ,  DOYLE PETER

IPC: G06T1/60 ,  G06F13/00 ,  G06T15/40 ,  G06T17/10

Abstract: A depth write disable apparatus and method for controlling evictions, such as depth values, from a depth cache to a corresponding depth buffer in a zone rendering system. When the depth write disable circuitry is enabled, evictions from the depth cache (as which typically occur during the rendering of the next zone) to the depth buffer are prevented. In particular, once the depth buffer is initialized (i.e. cleared) to a constant value at the beginning of a scene, the depth buffer does not need to be read. The depth cache handles intermediate depth reads and writes within each zone. Since the memory resident depth buffer is not required after a scene is rendered, it never needs to be written. The final depth values for a zone can thus be discarded (i.e., rather than written to the depth buffer) after each zone is rendering.

公开(公告)号：DE69625826D1

公开(公告)日：2003-02-20

申请号：DE69625826

申请日：1996-07-15

Applicant: INTEL CORP

Inventor： AJANOVIC JASMIN ,  MURDOCH N ,  DOBBINS M ,  SREENIVAS ADITYA ,  SAILER E ,  RABE L

IPC: G06F13/362 ,  G06F13/00 ,  G06F13/36

Abstract: A method and apparatus for regulating the deferral of a transaction issued on a bus by a processor in a computer system is disclosed. A bus transaction recorder coupled to the bus processes encoded signals from the transaction issued on the bus. A line coupled to the bus sends an indication signal when a pending transaction request is issued on the bus. A CPU latency timer times the current transaction on the bus when a new pending transaction is waiting on the bus. The CPU latency timer outputs an expiration signal when the transaction takes more than a predetermined amount of time to complete. A transaction processor unit is coupled to the bus transaction recorder, the line, and the CPU latency timer. The transaction processor unit defers the transactions issued on the bus when the transaction processor receives the indication signal indicating that a pending transaction is waiting to be issued on the bus, when the encoded signals from the transaction issued on the bus indicate that the transaction issued on the bus is a candidate for deferral, and when the CPU latency timer outputs the expiration signal.