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1.发明申请APPARATUS, METHOD AND SYSTEM WITH A GRAPHICS-RENDERING ENGINE HAVING A GRAPHICS CONTEXT MANAGER 审中-公开具有图形背景管理器的图形引擎的装置，方法和系统
公开(公告)号：WO03003206A2
公开(公告)日：2003-01-09
申请号：PCT/US0220682
申请日：2002-06-28
Applicant: INTEL CORP
Inventor： DOYLE PETER , SREENIVAS ADITYA
CPC classification number: G06F9/463
Abstract: A method, apparatus, and system to concurrently render independent images for display on one or more display devices. In an embodiment, a graphics-rendering engine concurrently renders independent images for display on multiple display devices. A graphics context manager stores in a first memory area and restores from the first memory area information describing a first rendering context associated with a first independent image. The graphics context manager stores in a second memory area and restores from the second memory area information describing a second rendering context associated with a second independent image.
Abstract translation: 一种同时呈现独立图像以在一个或多个显示设备上显示的方法，设备和系统。 在一个实施例中，图形渲染引擎同时渲染独立图像以在多个显示设备上显示。 图形上下文管理器存储在第一存储器区域中并且从第一存储器区域恢复描述与第一独立图像相关联的第一渲染上下文的信息。 图形上下文管理器存储在第二存储区域中，并且从第二存储区域恢复描述与第二独立图像相关联的第二渲染上下文的信息。
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公开(公告)号：WO0042594A9
公开(公告)日：2002-03-28
申请号：PCT/US0000776
申请日：2000-01-12
Applicant: INTEL CORP , DOYLE PETER , SREENIVAS ADITYA
Inventor： DOYLE PETER , SREENIVAS ADITYA
CPC classification number: G09G5/363 , G09G5/393 , G09G2360/122
Abstract: A method and apparatus for implementing a dynamic display memory is provided. A memory control hub suitable for interposition between a central processor and a memory includes a graphics memory control component. The graphics memory control component determines whether operands accessed by the central processor are graphics operands. If so, the graphics memory control component transforms the virtual address supplied by the central processor to a system address suitable for use in locating the graphics operand in the memory. In one embodiment, the graphics control component maintains a graphics translation table in the memory and utilizes the graphics translation table in transforming virtual addresses to system addresses. Furthermore, in one embodiment, the graphics control component reorders the addresses of the graphics operands to optimize for performance memory accesses by a graphics device.
Abstract translation: 提供了一种用于实现动态显示存储器的方法和装置。 适于中央处理器和存储器之间插入的存储器控制中心包括图形存储器控制部件。 图形存储器控制组件确定中央处理器访问的操作数是否是图形操作数。 如果是这样，则图形存储器控制部件将由中央处理器提供的虚拟地址转换成适合于将图形操作数定位在存储器中的系统地址。 在一个实施例中，图形控制组件在存储器中维护图形转换表，并利用图形转换表将虚拟地址转换成系统地址。 此外，在一个实施例中，图形控制部件重新排列图形操作数的地址以优化图形设备的性能存储器访问。
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公开(公告)号：AT469409T
公开(公告)日：2010-06-15
申请号：AT02794242
申请日：2002-12-11
Applicant: INTEL CORP
Inventor： SREENIVAS ADITYA , DOYLE PETER
Abstract: The present invention optimizes graphics performance during zone rendering by providing an automatic management of bin memory between the binning and rendering phases. Embodiments of the present invention provide a mechanism by which the binner and renderer automatically share a pool of physical memory pages in order to build bin buffers and recycle them after they have been used in rendering. This is performed in such a fashion that multiple binned scenes can be queued up concurrently, with no requirement for software intervention except under exceptional conditions. The need for software management of zone rendering bin buffer memory is thus eliminated. Multiple scenes for binning and rendering can also be queued without software intervention.
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公开(公告)号：AT422085T
公开(公告)日：2009-02-15
申请号：AT02795841
申请日：2002-12-11
Applicant: INTEL CORP
Inventor： SREENIVAS ADITYA , DOYLE PETER
Abstract: A depth write disable apparatus and method for controlling evictions, such as depth values, from a depth cache to a corresponding depth buffer in a zone rendering system. When the depth write disable circuitry is enabled, evictions from the depth cache (as which typically occur during the rendering of the next zone) to the depth buffer are prevented. In particular, once the depth buffer is initialized (i.e. cleared) to a constant value at the beginning of a scene, the depth buffer does not need to be read. The depth cache handles intermediate depth reads and writes within each zone. Since the memory resident depth buffer is not required after a scene is rendered, it never needs to be written. The final depth values for a zone can thus be discarded (i.e., rather than written to the depth buffer) after each zone is rendering.
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公开(公告)号：DE60231059D1
公开(公告)日：2009-03-19
申请号：DE60231059
申请日：2002-12-11
Applicant: INTEL CORP
Inventor： SREENIVAS ADITYA , DOYLE PETER
Abstract: A depth write disable apparatus and method for controlling evictions, such as depth values, from a depth cache to a corresponding depth buffer in a zone rendering system. When the depth write disable circuitry is enabled, evictions from the depth cache (as which typically occur during the rendering of the next zone) to the depth buffer are prevented. In particular, once the depth buffer is initialized (i.e. cleared) to a constant value at the beginning of a scene, the depth buffer does not need to be read. The depth cache handles intermediate depth reads and writes within each zone. Since the memory resident depth buffer is not required after a scene is rendered, it never needs to be written. The final depth values for a zone can thus be discarded (i.e., rather than written to the depth buffer) after each zone is rendering.
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Patent Agency Ranking
公开(公告)号：AU2002359689A1
公开(公告)日：2003-07-24
申请号：AU2002359689
申请日：2002-12-11
Applicant: INTEL CORP
Inventor： SREENIVAS ADITYA , DOYLE PETER
Abstract: The present invention optimizes graphics performance during zone rendering by providing an automatic management of bin memory between the binning and rendering phases. Embodiments of the present invention provide a mechanism by which the binner and renderer automatically share a pool of physical memory pages in order to build bin buffers and recycle them after they have been used in rendering. This is performed in such a fashion that multiple binned scenes can be queued up concurrently, with no requirement for software intervention except under exceptional conditions. The need for software management of zone rendering bin buffer memory is thus eliminated. Multiple scenes for binning and rendering can also be queued without software intervention.
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公开(公告)号：AU2002360575A1
公开(公告)日：2003-07-24
申请号：AU2002360575
申请日：2002-12-11
Applicant: INTEL CORP
Inventor： SREENIVAS ADITYA , DOYLE PETER
Abstract: A depth write disable apparatus and method for controlling evictions, such as depth values, from a depth cache to a corresponding depth buffer in a zone rendering system. When the depth write disable circuitry is enabled, evictions from the depth cache (as which typically occur during the rendering of the next zone) to the depth buffer are prevented. In particular, once the depth buffer is initialized (i.e. cleared) to a constant value at the beginning of a scene, the depth buffer does not need to be read. The depth cache handles intermediate depth reads and writes within each zone. Since the memory resident depth buffer is not required after a scene is rendered, it never needs to be written. The final depth values for a zone can thus be discarded (i.e., rather than written to the depth buffer) after each zone is rendering.
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公开(公告)号：DE112017004077T5
公开(公告)日：2019-08-22
申请号：DE112017004077
申请日：2017-08-15
Applicant: INTEL CORP
Inventor： SURTI PRASOONKUMAR , AKENINE-MOLLER TOMAS G , COWPERTHWAITE DAVID , TIAN KEVIN , DOYLE PETER , INSKO BRENT E , LAKE ADAM T
Abstract: Eine Einrichtung und ein Verfahren für eine virtuelle Realität werden für das kachelbasierte Rendering beschrieben. Beispielsweise umfasst eine Ausführungsform einer Einrichtung: einen Satz von On-Chip-Geometriepuffern, der einen ersten Puffer zum Speichern von Geometriedaten und einen Satz von Zeigerpuffern zum Speichern von Zeigern auf den Geometriedaten enthält; ein kachelbasiertes Sofortmodus-Rendering(TBIMR)-Modul, um ein kachelbasiertes Sofortmodus-Rendering unter Verwendung von Geometriedaten und Zeigern, die in dem Satz von On-Chip-Geometriepuffern gespeichert sind, durchzuführen; eine Überlaufschaltung, um zu bestimmen, wann die On-Chip-Geometriepuffer überzeichnet sind und ansprechend zusätzliche Geometriedaten und/oder Zeiger auf einen Off-Chip-Speicher auszuschütten; und einen Prefetcher, um damit zu beginnen, die Geometriedaten aus dem Off-Chip-Speicher im Voraus abzurufen, wenn innerhalb der On-Chip-Geometriepuffer Platz frei wird, wobei das TBIMR-Modul das kachelbasierte Sofortmodus-Rendering unter Verwendung der aus dem Off-Chip-Speicher im Voraus abgerufenen Geometriedaten durchführen soll.
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公开(公告)号：DE60236542D1
公开(公告)日：2010-07-08
申请号：DE60236542
申请日：2002-12-11
Applicant: INTEL CORP
Inventor： SREENIVAS ADITYA , DOYLE PETER
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公开(公告)号：DE60038871D1
公开(公告)日：2008-06-26
申请号：DE60038871
申请日：2000-01-12
Applicant: INTEL CORP
Inventor： DOYLE PETER , SREENIVAS ADITYA
Abstract: A method and apparatus for implementing a dynamic display memory is provided. A memory control hub suitable for interposition between a central processor and a memory includes a graphics memory control component. The graphics memory control component determines whether operands accessed by the central processor are graphics operands. If so, the graphics memory control component transforms the virtual address supplied by the central processor to a system address suitable for use in locating the graphics operand in the memory. In one embodiment, the graphics control component maintains a graphics translation table in the memory and utilizes the graphics translation table in transforming virtual addresses to system addresses. Furthermore, in one embodiment, the graphics control component reorders the addresses of the graphics operands to optimize for performance memory accesses by a graphics device.
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