公开(公告)号：SG11201704466QA

公开(公告)日：2017-07-28

申请号：SG11201704466Q

申请日：2015-12-14

Applicant: INTEL CORP

Inventor： VALENTINE ROBERT ,  HUGHES CHRISTOPHER J ,  CHARNEY MARK J ,  SPERBER ZEEV ,  GRADSTEIN AMIT ,  RUBANOVICH SIMON ,  GEBIL YURI ,  OULD-AHMED-VALL ELMOUSTAPHA

IPC: G06F15/80 ,  G06F9/38

Abstract: Instructions and logic provide SIMD vector packed tuple cross-comparison functionality. Some processor embodiments include first and second registers with a variable plurality of data fields, each of the data fields to store an element of a first data type. The processor executes a SIMD instruction for vector packed tuple cross-comparison in some embodiments, which for each data field of a portion of data fields in a tuple of the first register, compares its corresponding element with every element of a corresponding portion of data fields in a tuple of the second register and sets a mask bit corresponding to each element of the second register portion, in a bit-mask corresponding to each unmasked element of the corresponding first register portion, according to the corresponding comparison. In some embodiments bit-masks are shifted by corresponding elements in data fields of a third register. The comparison type is indicated by an immediate operand.