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    Combining instruction including instruction that performs sequence of transformation to isolate one transformation
    1.
    发明专利
    Combining instruction including instruction that performs sequence of transformation to isolate one transformation 有权
    组合指令，包括执行转换顺序以隔离一次转换的指令

    公开(公告)号：JP2009211071A

    公开(公告)日：2009-09-17

    申请号：JP2009045094

    申请日：2009-02-27

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： GUERON SHAY ,  SPERBER ZEEV

    IPC: G09C1/00

    CPC classification number: H04L9/0681 ,  G06F9/30007 ,  G06F21/75 ,  G06F2221/2107 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/125 ,  H04L2209/24

    Abstract: PROBLEM TO BE SOLVED: To provide the Advanced Encryption Standard (AES) that is a symmetric block cipher capable of encrypting and decrypting information. SOLUTION: Encryption (cipher) performs a series of transformations (Shift Rows, Substitute Bytes, Mix Columns) using a secret key (cipher key) to transform intelligible data referred to as "plaintext" into an unintelligible form referred to as "cipher text". The transformations (Inverse Shift Rows, Inverse Substitute Bytes, Inverse Mix Columns) in the inverse cipher (decryption) are the inverse of the transformations in the cipher. Encryption and decryption is performed efficiently through the use of instructions that perform the series of transformations. Combinations of these instructions allow the isolation of the transformations (Shift Rows, Substitute Bytes, Mix Columns, Inverse Shift Rows, Inverse Substitute Bytes, Inverse Mix Columns) to be obtained. COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：提供能够加密和解密信息的对称块密码的高级加密标准（AES）。 解决方案：加密（密码）使用秘密密钥（密码密钥）执行一系列转换（Shift Rows，Substitute Bytes，Mix Columns），将可被称为“明文”的可理解数据转换为一种不可理解的形式，称为“ 密文“。 反密码（解密）中的变换（逆位排，逆替换字节，反混合列）是密码中的变换的逆。 通过使用执行一系列转换的指令来有效地执行加密和解密。 这些指令的组合允许要获得的转换的隔离（Shift Rows，Substitution Bytes，Mix Columns，Inverse Shift Rows，Inverse Substitute Bytes，Inverse Mix Columns）。 版权所有（C）2009，JPO＆INPIT

    Method and apparatus for optimizing advanced encryption standard (aes) encryption and decryption in parallel mode of operation
    2.
    发明专利
    Method and apparatus for optimizing advanced encryption standard (aes) encryption and decryption in parallel mode of operation 有权
    用于优化并行运行模式下的高级加密标准（AES）加密和分解的方法和装置

    公开(公告)号：JP2009205161A

    公开(公告)日：2009-09-10

    申请号：JP2009043695

    申请日：2009-02-26

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： GUERON SHAY ,  GRADSTEIN AMIT ,  SPERBER ZEEV

    IPC: G09C1/00

    CPC classification number: H04L9/0631 ,  G06F9/30007 ,  H04L2209/125

    Abstract: PROBLEM TO BE SOLVED: To optimize advanced encryption standard (AES) encryption and decryption in parallel modes of operation.
    SOLUTION: The throughput of an encryption/decryption operation is increased in a system having a pipelined execution unit. Different independent encryptions (decryptions) of different data blocks may be performed in parallel by despatching an AES round instruction in each cycle.
    COPYRIGHT: (C)2009,JPO&INPIT

    Abstract translation: 要解决的问题：以并行运行模式优化先进的加密标准（AES）加密和解密。 解决方案：在具有流水线执行单元的系统中，加密/解密操作的吞吐量增加。 可以通过在每个周期中发送AES循环指令来并行地执行不同数据块的不同的独立加密（解密）。 版权所有（C）2009，JPO＆INPIT

    Efficient parallel floating point exception processing by processor
    3.
    发明专利
    Efficient parallel floating point exception processing by processor 审中-公开
    加工者有效的平行浮点处理

    公开(公告)号：JP2014002767A

    公开(公告)日：2014-01-09

    申请号：JP2013161489

    申请日：2013-08-02

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： SPERBER ZEEV ,  FINKELSTEIN SHACHAR ,  PRIBUSH GREGORY ,  GRADSTEIN AMIT ,  BALE GUY ,  PONS THIERRY

    IPC: G06F7/76 ,  G06F7/483 ,  G06F9/38

    CPC classification number: G06F9/3861 ,  G06F9/30014 ,  G06F9/30036

    Abstract: PROBLEM TO BE SOLVED: To efficiently process a floating point exception by a processor which executes an SIMD instruction.SOLUTION: Processing includes the steps of: specifying a numeral exception of an SIMD floating point operation; starting a first SIMD micro operation so as to generate a first Packed part result of the SIMD floating point operation; starting a second SIMD micro operation so as to generate a second Packed part result of the SIMD floating point operation; starting an SIMD unnormalization micro operation so as to put the first and second Packed part results together and to generate a third Packed result having an unnormalized element by unnormalizing a first element of the first and second Packed part results having been put together; storing the third Packed result of the SIMD floating point operation; and setting a flag for specifying the unnormalized element of the third Packed result to the first Packed part result.

    Abstract translation: 要解决的问题：通过执行SIMD指令的处理器有效地处理浮点异常。解决方案：处理包括以下步骤：指定SIMD浮点运算的数字异常; 开始第一SIMD微操作，以产生SIMD浮点运算的第一打包部分结果; 开始第二SIMD微操作，以产生SIMD浮点运算的第二打包部分结果; 开始SIMD非归一化微操作，以将第一和第二填充部分结果合并在一起，并通过将已经放在一起的第一和第二填充零件结果的第一元素非规范化来生成具有非归一化元素的第三填充结果; 存储SIMD浮点运算的第三个打包结果; 并且将用于将第三打包结果的非标准化元素指定为第一包装部分结果的标志。

    Efficient parallel floating-point exception handling in processor
    4.
    发明专利
    Efficient parallel floating-point exception handling in processor 审中-公开
    处理器中有效的平行浮点处理处理

    公开(公告)号：JP2010020761A

    公开(公告)日：2010-01-28

    申请号：JP2009152985

    申请日：2009-06-26

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： SPERBER ZEEV ,  FINKELSTEIN SHACHAR ,  PRIBUSH GREGORY ,  GRADSTEIN AMIT ,  BALE GUY ,  PONS THIERRY

    IPC: G06F7/00

    CPC classification number: G06F9/3861 ,  G06F9/30014 ,  G06F9/30036

    Abstract: PROBLEM TO BE SOLVED: To efficiently handle floating-point exceptions in a processor that executes single-instruction multiple-data (SIMD) instructions. SOLUTION: A method is provided for handling the floating-point exceptions in the processor that executes the SIMD instructions. The method includes: a step of initiating a first SIMD micro-operation to generate first packed partial results of the SIMD operation; a step of initiating a second SIMD micro-operation to generate second packed partial results of the SIMD operation; a step of initiating a SIMD denormalization micro-operation to combine the first and the second packed partial results and to generate third packed results having denormalized elements by denormalizing a first element of first and second packed partial results; a step of storing third packed results of the SIMD operation; and a step of setting a flag to identify denormalized elements of the third packed results in the first packed partial results. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：有效处理执行单指令多数据（SIMD）指令的处理器中的浮点异常。 解决方案：提供了一种处理执行SIMD指令的处理器中的浮点异常的方法。 该方法包括：启动第一SIMD微操作以产生SIMD操作的第一打包部分结果的步骤; 启动第二SIMD微操作以产生SIMD操作的第二打包部分结果的步骤; 启动SIMD非规范化微操作以组合第一和第二打包部分结果并通过对第一和第二打包部分结果的第一元素进行非归一化来生成具有非归一化元素的第三打包结果的步骤; 存储SIMD操作的第三打包结果的步骤; 以及设置标志以识别第一打包部分结果中的第三打包结果的非规范化元素的步骤。 版权所有（C）2010，JPO＆INPIT

    Efficient parallel floating point exception handling in processor
    5.
    发明专利
    Efficient parallel floating point exception handling in processor 审中-公开
    处理器中有效的平行浮点处理处理

    公开(公告)号：JP2013050965A

    公开(公告)日：2013-03-14

    申请号：JP2012222612

    申请日：2012-10-05

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： SPERBER ZEEV ,  FINKELSTEIN SHACHAR ,  PRIBUSH GREGORY ,  GRADSTEIN AMIT ,  BALE GUY ,  PONS THIERRY

    IPC: G06F7/76 ,  G06F9/38

    CPC classification number: G06F9/3861 ,  G06F9/30014 ,  G06F9/30036

    Abstract: PROBLEM TO BE SOLVED: To efficiently handle floating point exceptions in a processor that executes SIMD instructions.SOLUTION: The method comprising: identifying a numerical exception for a SIMD floating point operation; initiating a first SIMD micro-operation to generate a first packed partial result for the SIMD floating point operation; initiating a second SIMD micro-operation to generate a second packed partial result for the SIMD floating point operation; initiating a SIMD denormalization micro-operation to combine the first and second packed partial results and to denormalize a first element of the combined first and second packed partial results to generate a third packed result having a denormal element; storing the third packed result for the SIMD floating point operation; and setting a flag identifying the denormal element of the third packed result in the first packed partial result.

    Abstract translation: 要解决的问题：有效处理执行SIMD指令的处理器中的浮点异常。 解决方案：该方法包括：识别SIMD浮点运算的数字异常; 启动第一SIMD微操作以产生用于SIMD浮点运算的第一打包部分结果; 启动第二SIMD微操作以产生用于SIMD浮点运算的第二打包部分结果; 启动SIMD非规范化微操作以组合所述第一和第二打包部分结果，并且对所述组合的第一和第二打包部分结果的第一元素进行非规范化，以生成具有反正态元素的第三打包结果; 存储用于SIMD浮点运算的第三打包结果; 以及在第一打包部分结果中设置标识第三打包结果的异常元素的标志。 版权所有（C）2013，JPO＆INPIT

    DUAL CACHE WITH MULTIPLE INTERCONNECTION OPERATION
    6.
    发明申请
    DUAL CACHE WITH MULTIPLE INTERCONNECTION OPERATION 审中-公开
    具有多个互连操作的双缓存

    公开(公告)号：WO0150267A3

    公开(公告)日：2001-11-22

    申请号：PCT/US0030577

    申请日：2000-11-07

    Applicant: INTEL CORP

    Inventor： SPERBER ZEEV ,  DOWECK JACK D ,  KACEVAS NICOLAS ,  NESHER ROY

    IPC: G06F12/08

    CPC classification number: G06F12/0897

    Abstract: A computer system having cache modules interconnected in series includes a first and a second cache module directly coupled to an address generating line for parallel lookup of data and data conversion logic coupled between the first cache module and said second cache module.

    Abstract translation: 具有串联互连的高速缓存模块的计算机系统包括直接耦合到地址生成线的第一和第二高速缓存模块，用于对耦合在第一高速缓存模块和第二高速缓存模块之间的数据和数据转换逻辑进行并行查找。

    POWER AWARE RETIREMENT
    9.
    发明申请
    POWER AWARE RETIREMENT 审中-公开
    功率损失

    公开(公告)号：WO2009158247A3

    公开(公告)日：2010-03-04

    申请号：PCT/US2009047613

    申请日：2009-06-17

    Applicant: INTEL CORP ,  SPERBER ZEEV ,  MAROM RAFI ,  LEVY OFER

    Inventor： SPERBER ZEEV ,  MAROM RAFI ,  LEVY OFER

    IPC: G06F9/44 ,  G06F1/26 ,  G06F9/30 ,  G06F13/14

    CPC classification number: G06F1/3203 ,  G06F1/3287 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3865 ,  Y02D10/124 ,  Y02D10/171 ,  Y02D50/20

    Abstract: In one embodiment, the present invention includes a retirement unit to receive and retire executed instructions. The retirement unit may include a first array to receive information at allocation and a second array to receive information after execution. The retirement unit may further include logic to calculate an event associated with an executed instruction if information associated with the executed instruction is stored in an on-demand portion of at least one of arrays. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括用于接收和退出执行的指令的退休单元。 退休单元可以包括用于在分配时接收信息的第一阵列和用于在执行之后接收信息的第二阵列。 如果与所执行的指令相关联的信息被存储在阵列中的至少一个的按需部分中，退休单元还可以包括用于计算与执行的指令相关联的事件的逻辑。 描述和要求保护其他实施例。

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