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公开(公告)号：JP2011181094A
公开(公告)日：2011-09-15
申请号：JP2011106136
申请日：2011-05-11
Applicant: Intel Corp , インテル コーポレイション
Inventor： BRANDT JASON , MONDAL SANJOY K , UHLIG RICHARD , NEIGER GILBERT , GEORGE ROBERT
CPC classification number: G06F12/1027 , G06F9/45533 , G06F9/45558 , G06F9/4843 , G06F12/0292 , G06F12/0804 , G06F12/0891 , G06F12/1036 , G06F12/1063 , G06F12/109 , G06F12/12 , G06F12/123 , G06F2009/45583 , G06F2009/45591 , G06F2212/1016 , G06F2212/152 , G06F2212/30 , G06F2212/50 , G06F2212/604 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/684 , G06F2212/69
Abstract: PROBLEM TO BE SOLVED: To reduce the overhead associated with switching the context of an address space. SOLUTION: This method includes: a step of switching the context between the first address space and the second address space by the processor of a system; a step of determining whether the second address space exists in a list of address spaces stored in a scratch pad memory of the processor; a step of allocating a new entry of the second address space that is different from the current entry of the first address space after switching the context to the second address space if the second address space does not exist in the list of address spaces; and a step of maintaining the current entry of the first address space to a conversion buffer of the processor after switching the context to the second address space if the second address space exists in the list of address space. COPYRIGHT: (C)2011,JPO&INPIT
Abstract translation: 要解决的问题：减少与切换地址空间的上下文相关的开销。 解决方案：该方法包括：由系统的处理器切换第一地址空间和第二地址空间之间的上下文的步骤; 确定第二地址空间是否存在于存储在处理器的临时存储器存储器中的地址空间的列表中的步骤; 如果第二地址空间不存在于地址空间列表中，则将上下文切换到第二地址空间之后，分配与第一地址空间的当前条目不同的第二地址空间的新条目的步骤; 以及如果第二地址空间存在于地址空间列表中，则在将上下文切换到第二地址空间之后，将第一地址空间的当前条目保持到处理器的转换缓冲器的步骤。 版权所有（C）2011，JPO＆INPIT
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公开(公告)号：JP2011023017A
公开(公告)日：2011-02-03
申请号：JP2010179219
申请日：2010-08-10
Applicant: Intel Corp , インテル コーポレイション
Inventor： BRANDT JASON , MONDAL SANJOY K , UHLIG RICHARD , NEIGER GILBERT , GEORGE ROBERT
IPC: G06F12/10
CPC classification number: G06F12/1027 , G06F9/45533 , G06F9/45558 , G06F9/4843 , G06F12/0292 , G06F12/0804 , G06F12/0891 , G06F12/1036 , G06F12/1063 , G06F12/109 , G06F12/12 , G06F12/123 , G06F2009/45583 , G06F2009/45591 , G06F2212/1016 , G06F2212/152 , G06F2212/30 , G06F2212/50 , G06F2212/604 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/684 , G06F2212/69
Abstract: PROBLEM TO BE SOLVED: To reduce flush of a TLB (Translation Lookaside Buffer) and another pipeline to be the cause of generating overhead in a context switch in a virtual machine (VM) environment or another environment.
SOLUTION: Switching is made between guest software and a virtual machine monitor, whether storage in a protected location causes the switching is determined, and at least one entry of processor resources corresponding to the protected location is selectively flushed while maintaining another entry of processor resources corresponding to the guest software.
COPYRIGHT: (C)2011,JPO&INPITAbstract translation: 要解决的问题：减少TLB（翻译后备缓冲区）和另一个流水线的刷新，从而成为在虚拟机（VM）环境或其他环境中的上下文切换中产生开销的原因。 解决方案：在客户软件和虚拟机监视器之间进行切换，无论存储在受保护的位置是否导致切换，并且选择性地刷新与受保护位置相对应的处理器资源的至少一个条目，同时保持 对应于客户软件的处理器资源。 版权所有（C）2011，JPO＆INPIT
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公开(公告)号：JP2011008805A
公开(公告)日：2011-01-13
申请号：JP2010179220
申请日：2010-08-10
Applicant: Intel Corp , インテル コーポレイション
Inventor： BRANDT JASON , MONDAL SANJOY K , UHLIG RICHARD , NEIGER GILBERT , GEORGE ROBERT
IPC: G06F12/10
CPC classification number: G06F12/1027 , G06F9/45533 , G06F9/45558 , G06F9/4843 , G06F12/0292 , G06F12/0804 , G06F12/0891 , G06F12/1036 , G06F12/1063 , G06F12/109 , G06F12/12 , G06F12/123 , G06F2009/45583 , G06F2009/45591 , G06F2212/1016 , G06F2212/152 , G06F2212/30 , G06F2212/50 , G06F2212/604 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/684 , G06F2212/69
Abstract: PROBLEM TO BE SOLVED: To reduce the number of flushes of pipeline resources on context switches and effectively maintain the pipeline resources, in consideration that context switches in a VM or other environment needs flushes of TLBs and the pipeline resources, and overhead can adversely impact performance, especially in systems with many active contexts.SOLUTION: The method includes steps of: determining whether a predetermined command changes a selected value or not; performing operations with the processor resources if the selected value is not changed; and flushing all entries in all address spaces of the processor resources if the selected value has been changed.
Abstract translation: 要解决的问题：为了减少上下文切换中管道资源的刷新次数，并有效维护流水线资源，考虑到VM或其他环境中的上下文切换需要刷新TLB和管道资源，并且开销可能会对性能产生不利影响 特别是在具有许多活动环境的系统中。解决方案：该方法包括以下步骤：确定预定命令是否改变所选择的值; 如果所选择的值不被改变，则用处理器资源执行操作; 并且如果所选择的值已被更改，则刷新处理器资源的所有地址空间中的所有条目。
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公开(公告)号：JP2011181095A
公开(公告)日：2011-09-15
申请号：JP2011106137
申请日：2011-05-11
Applicant: Intel Corp , インテル コーポレイション
Inventor： BRANDT JASON , MONDAL SANJOY K , UHLIG RICHARD , NEIGER GILBERT , GEORGE ROBERT
CPC classification number: G06F12/1027 , G06F9/45533 , G06F9/45558 , G06F9/4843 , G06F12/0292 , G06F12/0804 , G06F12/0891 , G06F12/1036 , G06F12/1063 , G06F12/109 , G06F12/12 , G06F12/123 , G06F2009/45583 , G06F2009/45591 , G06F2212/1016 , G06F2212/152 , G06F2212/30 , G06F2212/50 , G06F2212/604 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/684 , G06F2212/69
Abstract: PROBLEM TO BE SOLVED: To reduce overhead associated with switching the context of an address space. SOLUTION: A processor includes: a control register which stores an address based on a page directory corresponding to the address space; a conversion look-aside buffer which includes an entry containing a field of an address space identifier; and an execution logic which executes an "MOV to control register" command in order to switch between the address spaces without flashing the conversion look-aside buffer. COPYRIGHT: (C)2011,JPO&INPIT
Abstract translation: 要解决的问题：减少与切换地址空间的上下文相关的开销。 解决方案：处理器包括：控制寄存器，其基于与地址空间相对应的页目录来存储地址; 转换后备缓冲器，其包括包含地址空间标识符的字段的条目; 以及执行“MOV到控制寄存器”命令以便在地址空间之间切换而不闪烁转换后备缓冲器的执行逻辑。 版权所有（C）2011，JPO＆INPIT
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公开(公告)号：JP2007265434A
公开(公告)日：2007-10-11
申请号：JP2007150997
申请日：2007-06-06
Applicant: Intel Corp , インテル コーポレイション
Inventor： SUTTON II JAMES , GRAWROCK DAVID , UHLIG RICHARD , POISNER DAVID , GLEW ANDREW , HALL CLIFFORD , SMITH III LAWRENCE , NEIGER GILBERT , KOZUCH MICHAEL , GEORGE ROBERT , BURGESS BRADLEY
CPC classification number: G06F21/53 , G06F12/1491 , G06F21/57 , G06F2221/2105
Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for allowing execution of a system management mode (SMM) code during secure operations in a microprocessor system. SOLUTION: In one embodiment, a system management interruption (SMI) may be first directed to a handler in a secured virtual machine monitor (SVMM). The SMI may then be re-directed to an SMM code located in a virtual machine (VM) that is under the security control of the SVMM. This redirection can be accomplished by allowing reading from and writing to the system management (SM) base register in the processor. COPYRIGHT: (C)2008,JPO&INPIT
Abstract translation: 要解决的问题：提供一种用于在微处理器系统中的安全操作期间允许执行系统管理模式（SMM）代码的系统和方法。 解决方案：在一个实施例中，可以将系统管理中断（SMI）首先定向到安全虚拟机监视器（SVMM）中的处理程序。 然后，SMI可以被重定向到位于SVMM的安全控制下的虚拟机（VM）中的SMM代码。 这种重定向可以通过读取和写入处理器中的系统管理（SM）基址寄存器来实现。 版权所有（C）2008，JPO＆INPIT
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Patent Agency Ranking
公开(公告)号：WO2006019914A3
公开(公告)日：2006-06-22
申请号：PCT/US2005024997
申请日：2005-07-14
Applicant: INTEL CORP , BRANDT JASON , MONDAL SANJOY K , UHLIG RICHARD , NEIGER GILBERT , GEORGE ROBERT
Inventor： BRANDT JASON , MONDAL SANJOY K , UHLIG RICHARD , NEIGER GILBERT , GEORGE ROBERT
CPC classification number: G06F12/1027 , G06F9/45533 , G06F9/45558 , G06F9/4843 , G06F12/0292 , G06F12/0804 , G06F12/0891 , G06F12/1036 , G06F12/1063 , G06F12/109 , G06F12/12 , G06F12/123 , G06F2009/45583 , G06F2009/45591 , G06F2212/1016 , G06F2212/152 , G06F2212/30 , G06F2212/50 , G06F2212/604 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/684 , G06F2212/69
Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.
Abstract translation: 在本发明的一个实施例中，一种方法包括在第一地址空间和第二地址空间之间切换，确定地址空间列表中是否存在第二地址空间; 并且在切换之后保持翻译缓冲器中的第一地址空间的条目。 以这种方式，可以减少与这种上下文切换相关联的开销。
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公开(公告)号：HK1101436A1
公开(公告)日：2007-10-18
申请号：HK07109284
申请日：2007-08-27
Applicant: INTEL CORP
Inventor： BRANDT JASON , MONDAL SANJOY K , UHLIG RICHARD , NEIGER GILBERT , GEORGE ROBERT
IPC: G06F20060101
Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.
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公开(公告)号：AU2002357343A1
公开(公告)日：2003-07-24
申请号：AU2002357343
申请日：2002-12-18
Applicant: INTEL CORP
Inventor： BLAKENSHIP ROBERT , GEORGE ROBERT , CRETA KENNETH
Abstract: Apparatus having a cache memory including cache lines configured to cache data sent from an input/output device and an eviction mechanism configured to evict data stored in one of the cache lines based on validity state information associated with the data stored in the one cache line. Each cache line has multiple portions, and validity bits are used to track the validity of respective portions of the cache line. The validity bits are set to predefined values responsive to the number of bytes written into the respective portions in one write transaction. The cache line is evicted by the eviction mechanism when the validity bits corresponding to the cache line all have the predefined values. The eviction mechanism is configured to evict the data even if the cache memory is not full.
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公开(公告)号：DE112005003859B4
公开(公告)日：2022-01-27
申请号：DE112005003859
申请日：2005-07-14
Applicant: INTEL CORP
Inventor： GEORGE ROBERT , NEIGER GILBERT , BRANDT JASON , MONDAL SANJOY K , UHLIG RICHARD
IPC: G06F12/10
Abstract: Prozessor (401), aufweisend:einen Übersetzungspuffer, TLB, (403); undein Adressraumidentifizier-, ASID, -Register (405) zum Speichern eines ersten ASID-Wertes, der mit einem ersten Adressraum (30) assoziiert ist;wobei der TLB (403) einen ersten Eintrag (300), aufweisend eine erste virtuelle Adresse, eine erste physikalische Adresse und den ersten ASID-Wert, speichert, und wobei der TLB (403) auch einen zweiten Eintrag (300), aufweisend eine zweite virtuelle Adresse, eine zweite physikalische Adresse, und einen zweiten ASID-Wert, speichert, der mit einem zweiten Adressraum (40) assoziiert ist; undwobei der Prozessor (401) den zweiten ASID-Wert im ASID-Register während einer Kontextumschaltung (55) vom ersten Adressraum (30) zum zweiten Adressraum (40) ohne ein Entleeren des ersten Eintrags (300) aus dem TLB (403) speichert.
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公开(公告)号：AU2003231237A8
公开(公告)日：2003-12-22
申请号：AU2003231237
申请日：2003-05-01
Applicant: INTEL CORP
Inventor： GRAWROCK DAVID , GEORGE ROBERT , HALL CLIFFORD , SMITH LAWRENCE III , SUTTON JAMES II , BURGESS BRADLEY , POISNER DAVID , NEIGER GILBERT , UHLIG RICHARD , KOZUCH MICHAEL , GLEW ANDREW
Abstract: Techniques for handling certain virtualization events occurring within a virtual machine environment. More particularly, at least one embodiment of the invention pertains to handling events related to the sub-operating system mode using a dedicated virtual machine monitor (VMM) called the system management mode VMM (SVMM), which exists in a separate portion of memory from a main virtual machine monitor (MVMM) used to handle virtualization events other than those related to the sub-operating system mode. In at least one embodiment, a technique for initializing and managing transitions to and from the SVMM is disclosed.
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