公开(公告)号：JP2007265434A

公开(公告)日：2007-10-11

申请号：JP2007150997

申请日：2007-06-06

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： SUTTON II JAMES ,  GRAWROCK DAVID ,  UHLIG RICHARD ,  POISNER DAVID ,  GLEW ANDREW ,  HALL CLIFFORD ,  SMITH III LAWRENCE ,  NEIGER GILBERT ,  KOZUCH MICHAEL ,  GEORGE ROBERT ,  BURGESS BRADLEY

IPC: G06F1/00 ,  G06F21/22 ,  G06F9/46 ,  G06F9/48 ,  G06F12/14 ,  G06F21/00

CPC classification number: G06F21/53 ,  G06F12/1491 ,  G06F21/57 ,  G06F2221/2105

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method for allowing execution of a system management mode (SMM) code during secure operations in a microprocessor system. SOLUTION: In one embodiment, a system management interruption (SMI) may be first directed to a handler in a secured virtual machine monitor (SVMM). The SMI may then be re-directed to an SMM code located in a virtual machine (VM) that is under the security control of the SVMM. This redirection can be accomplished by allowing reading from and writing to the system management (SM) base register in the processor. COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于在微处理器系统中的安全操作期间允许执行系统管理模式（SMM）代码的系统和方法。 解决方案：在一个实施例中，可以将系统管理中断（SMI）首先定向到安全虚拟机监视器（SVMM）中的处理程序。 然后，SMI可以被重定向到位于SVMM的安全控制下的虚拟机（VM）中的SMM代码。 这种重定向可以通过读取和写入处理器中的系统管理（SM）基址寄存器来实现。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：WO02054257A3

公开(公告)日：2003-09-04

申请号：PCT/US0150576

申请日：2001-12-21

Applicant: INTEL CORP

Inventor： POISNER DAVID ,  OOI THIEN ERN

IPC: G06F13/24 ,  G06F3/06

CPC classification number: G06F13/24

Abstract: An apparatus for sharing an interrupt between a controller for a parallel storage device interface and a controller for a serial storage device interface includes interrupt conditioning circuitry that masks an interrupt signal coming from the parallel storage device interface if no storage device is coupled to the parallel storage device interface. The masking of the parallel storage device interface interrupt of no storage device is coupled to the parallel storage device interface allows the controller for the serial storage device interface to share the interrupt traditionally assigned to the parallel storage device interface.

Abstract translation: 用于在用于并行存储设备接口的控制器和用于串行存储设备接口的控制器之间共享中断的设备包括：中断调节电路，其屏蔽来自并行存储设备接口的中断信号，如果没有存储设备耦合到并行存储器 设备接口 没有存储设备的并行存储设备接口中断的屏蔽耦合到并行存储设备接口，允许串行存储设备接口的控制器共享传统分配给并行存储设备接口的中断。

公开(公告)号：WO03096170A2

公开(公告)日：2003-11-20

申请号：PCT/US0310428

申请日：2003-04-02

Applicant: INTEL CORP

Inventor： CUI YING ,  SAMSON ERIC ,  BERKOVITS ARIEL ,  NAVALE ADITYA ,  WYATT DAVID ,  CLINE LESLIE ,  TSANG JOSEPH ,  BLAKE MARK ,  POISNER DAVID ,  STEVENS WILLIAM JR ,  SAR-DESSAI VIJAY

IPC: G06F1/04 ,  G06F1/32

CPC classification number: G06F1/3228 ,  G06F1/3215 ,  G06F1/324 ,  G06F1/325 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment of the invention, an integrated device is described that employs a mechanism to control power consumption of a graphics memory controller hub (GMCH) through both voltage and frequency adjustment of clock signal received from a clock generator. The GMCH comprises a graphics core and a circuit to alter operational behavior, such as the frequency of a render clock signal supplied to the graphics core. The circuit is adapted to monitor idleness of the graphics core and reduce a frequency level of the render clock signal if the idleness exceeds a determined percentage of time.

Abstract translation: 在本发明的一个实施例中，描述了一种集成装置，其采用机制来通过从时钟发生器接收的时钟信号的电压和频率调整来控制图形存储器控制器集线器（GMCH）的功率消耗。 GMCH包括图形核心和改变操作行为的电路，例如提供给图形核心的渲染时钟信号的频率。 该电路适用于监视图形核心的空闲，并且如果闲置时间超过确定的时间百分比，则降低渲染时钟信号的频率水平。

公开(公告)号：WO2004095298A3

公开(公告)日：2005-02-10

申请号：PCT/US2004004220

申请日：2004-02-11

Applicant: INTEL CORP

Inventor： POISNER DAVID

IPC: G06F13/00 ,  G06F13/14 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F13/4243 ,  G11C5/066

Abstract: Apparatus and method for providing a multiplexed bus supporting the coupling of either one of a device having a first bus type interface and a device having a second bus type interface where the multiplexed bus is made up, at least in part, of a plurality of common signal lines that may be coupled to either type of device, and that may be used to carry out transfers with protocols and timings for either bus.

Abstract translation: 一种用于提供多路复用总线的装置和方法，所述多路复用总线支持具有第一总线类型接口的设备中的任一个的耦合，以及具有第二总线类型接口的设备，所述多路复用总线至少部分地由多个公共端 信号线可以耦合到任一类型的设备，并且可以用于对任一总线的协议和时序执行传输。

公开(公告)号：WO2006060237A3

公开(公告)日：2006-09-14

申请号：PCT/US2005042314

申请日：2005-11-17

Applicant: INTEL CORP ,  POISNER DAVID ,  STEVENS WILLIAM

Inventor： POISNER DAVID ,  STEVENS WILLIAM

IPC: G06F11/14

CPC classification number: G06F11/1441 ,  G06F12/0804

Abstract: In some embodiment, an arrangement is provided to prevent a loss of data in a memory due to a power failure for a computing system. When the power failure occurs, any pending memory write operations may be completed and dirty cache lines may be flushed back to the memory. Subsequently, the computing system may be put into a loss-prevention state, under which power may be turned off for all components in the computing system except the memory. The memory is powered by a battery pack which includes batteries and is in a self refresh state. When the power returns, applications and operating systems running in the computing system may resume what is left out when the power supply failure occurs, based at least in part on data retained in the memory. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，提供了一种布置，以防止由于计算系统的电源故障导致的存储器中的数据丢失。 当发生电源故障时，可能会完成任何未完成的存储器写操作，并将脏高速缓存行刷新回存储器。 随后，计算系统可以被置于防止丢失状态，在该状态下，计算系统中除了存储器之外的所有组件都可以关闭电源。 存储器由包括电池并且处于自刷新状态的电池组供电。 当电力返回时，运行在计算系统中的应用程序和操作系统可以至少部分地基于保存在存储器中的数据来恢复发生电源故障时所剩下的内容。 描述和要求保护其他实施例。

公开(公告)号：WO2004042587A3

公开(公告)日：2004-10-07

申请号：PCT/US0333734

申请日：2003-10-23

Applicant: INTEL CORP

Inventor： POISNER DAVID

IPC: G06F13/24 ,  G06F1/22

CPC classification number: G06F13/24 ,  Y02D10/14

Abstract: Machine-readable media, methods, and apparatus are described for event deliver. In some embodiments, a virtual wire message is generated in response to an event. The virtual wire message may comprise a header providing destination and message type information. The virtual wire message may further comprise a payload providing status information for one or more events.

Abstract translation: 描述了用于事件传递的机器可读介质，方法和装置。 在一些实施例中，响应于事件产生虚拟有线消息。 虚拟有线消息可以包括提供目的地和消息类型信息的报头。 虚拟线路消息还可以包括用于一个或多个事件的有效载荷提供状态信息。

公开(公告)号：WO2008005813A2

公开(公告)日：2008-01-10

申请号：PCT/US2007072425

申请日：2007-06-28

Applicant: INTEL CORP ,  POISNER DAVID

Inventor： POISNER DAVID

CPC classification number: H02J7/0045

Abstract: The embodiments of the invention relate to a novel apparatus and method for a battery charging system in a shared environment, as well as for monitoring battery usage and tracking battery location. In one embodiment, the battery charging chute comprises a housing configured to receive a battery via an insertion slot and configured to dispense a battery through a dispensing slot. Within the housing, charging terminals are disposed is a spaced or continuous manner, to come in contact with the charging terminals on batteries inserted into the housing. Optionally, solenoid-controlled gates may be employed at the insertion slot and dispensing slot, to inhibit the removal or insertion of batteries from the incorrect location, to ensure that the battery with the longest residence time in the chute is dispensed to a user. The housing may also include a radio-frequency identification tag reader to permit inventorying and tracking of batteries inserted into the housing.

Abstract translation: 本发明的实施例涉及一种用于共享环境中的电池充电系统的新型装置和方法，以及用于监视电池使用和跟踪电池位置。 在一个实施例中，电池充电斜槽包括被配置为经由插槽接收电池并被配置为通过分配槽分配电池的壳体。 在壳体内，充电端子被设置为间隔的或连续的方式，以便与插入壳体的电池上的充电端子接触。 可选地，可以在插入槽和分配槽处采用螺线管控制的门，以阻止电池从不正确的位置移除或插入，以确保在滑道中具有最长停留时间的电池被分配给使用者。 壳体还可以包括射频识别标签读取器，以允许对插入到壳体中的电池进行库存和跟踪。

公开(公告)号：WO2004003711A2

公开(公告)日：2004-01-08

申请号：PCT/US0319597

申请日：2003-06-20

Applicant: INTEL CORP

Inventor： GRAWCOCK DAVID ,  POISNER DAVID

IPC: G06F21/24 ,  G06F1/00 ,  G06F21/00

CPC classification number: G06F21/57 ,  G06F21/79

Abstract: Methods, apparatus and machine-readable medium are described that attempt to protect secrets from sleep attacks. In some embodiments, the secrets are encrypted and a security enhanced environment dismantled prior to entering a sleep state. Some embodiments further re-establish a security enhanced environment and decrypt the secrets in response to a wake event.

Abstract translation: 描述了尝试保护秘密免于睡眠攻击的方法，装置和机器可读介质。 在一些实施例中，秘密被加密，并且在进入睡眠状态之前拆除安全增强的环境。 一些实施例进一步重新建立安全增强环境并且响应于唤醒事件来解密秘密。

公开(公告)号：EP3074817A4

公开(公告)日：2017-07-12

申请号：EP13898386

申请日：2013-11-29

Applicant: INTEL CORP

Inventor： CHENG LIANG ,  MA LILI ,  HAN HEMIN ,  POISNER DAVID ,  QUIET DUANE

IPC: G06F3/01 ,  G03B17/00 ,  G06K9/00 ,  H04N5/232 ,  H04N5/247

CPC classification number: H04N5/23219 ,  G06F3/011 ,  G06F3/012 ,  G06F3/017 ,  G06K9/00221 ,  G06K9/00255 ,  G06K9/00335 ,  G06K9/6202 ,  H04N5/23216 ,  H04N5/247

公开(公告)号：AT413656T

公开(公告)日：2008-11-15

申请号：AT03790482

申请日：2003-12-11

Applicant: INTEL CORP

Inventor： POISNER DAVID

IPC: G06F21/02 ,  G06F1/14 ,  G06F21/00

Abstract: Methods, apparatus and computer readable medium are described that attempt increase trust in a system time provided by a system clock. In some embodiments, a detector detects activities that may be associated with attacks against the system clock. Based upon whether the detector detects a possible attack against the system clock, the computing device may determine whether or not to trust the system time provided by the system clock.