公开(公告)号：JP2006185453A

公开(公告)日：2006-07-13

申请号：JP2006009928

申请日：2006-01-18

Applicant: INTEL CORP

Inventor： LIN DERRICK ,  VAKKALAGADDA ROMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI HIDEKAZU ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/305 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

Abstract: PROBLEM TO BE SOLVED: To incorporate a set of instructions for processing packed data in a processor so as to have compatibility with existing software and hardware. SOLUTION: Both of a set of packed data instructions are performed before performance of floating point instruction to contents of a single logic register file which is at least partially aliased and to which a plurality of tags correspond, at a point of time between staring of performance of a first instruction of the packed data instruction set and completion of performance of a first instruction of a floating point instruction set, the plurality of tags corresponding to the aliased register in at least a single logic register file are changed to a not empty state and the tag identifies whether or not the register in the single logic register file is empty. COPYRIGHT: (C)2006,JPO&NCIPI

公开(公告)号：JP2004152319A

公开(公告)日：2004-05-27

申请号：JP2003417826

申请日：2003-12-16

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： LIN DERRICK ,  VAKKALAGADDA ROMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI HIDEKAZU ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: PROBLEM TO BE SOLVED: To use a single physical register file under an alias to execute a floating point instruction and a pack data instruction. SOLUTION: A first instruction is received, it is determined whether the first instruction is the floating point instruction or a second type instruction, and it is determined whether a processor including first and second pairs of physical registers is in a floating point mode or in a second type mode. If the processor is in the second type mode when the first instruction is the floating point instruction, transition to the floating point mode is carried out, and the floating point instruction is operated by using the first pair of physical registers. If the processor is not in the floating point mode, transition to the second type mode is carried out, and the second type instruction is operated by using the second pair of physical registers partially under an alias to the first pair of physical registers so that the first pair of physical registers and the second pair of physical registers appear to be a single logical register file logically. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004152318A

公开(公告)日：2004-05-27

申请号：JP2003417823

申请日：2003-12-16

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： LIN DERRICK ,  VAKKALAGADDA ROMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI HIDEKAZU ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: PROBLEM TO BE SOLVED: To install a set of instructions in a processor for processing pack data for furnishing compatibility with existing software and hardware. SOLUTION: For executing both of a set of pack data instructions and a set of floating point instructions on contents, which are aliased partially at least and correspond to a plurality of tags, of a single logical register file, the set of pack data instructions are executed before execution of the set of floating point instructions. At a certain time between a start of execution of a first instruction in the set of pack data instructions and execution of a first instruction in the set of floating point instructions, a plurality of tags matching an alias register in at least a single logical register file are changed into a non-empty condition, and the tags determine whether the register in a signal logical register file is empty or not. COPYRIGHT: (C)2004,JPO

公开(公告)号：WO0206929A2

公开(公告)日：2002-01-24

申请号：PCT/US0122027

申请日：2001-07-13

Applicant: INTEL CORP

Inventor： GOLLIVER ROGER ,  SUTTON JAMES II ,  LIN DERRICK ,  THAKKAR SHREEKANT ,  NEIGER GILBERT ,  MCKEEN FRANCIS ,  HERBERT HOWARD ,  RENERIS KENNETH ,  ELLISON CARL

IPC: G06F12/14 ,  G06F1/00

CPC classification number: G06F12/1475

Abstract: The present invention provides a method, apparatus, and system for controlling memory accesses to multiple isolated memory areas in an isolated execution environment. A page manager is used to distribute a plurality of pages to a plurality of different areas of a memory, respectively. The memory is divided into non-isolated areas and isolated areas. The page manager is located in an isolated area of memory. Further, a memory ownership page table describes each page of memory and is also located in an isolated area of memory. The page manager assigns an isolated attribute to a page if the page is distributed to an isolated are of memory. On the other hand, the page manager assigns a non-isolated attribute to a page if the page is distributed to a non-isolated area of memory. The memory ownership page table records the attribute for each page. In one embodiment, a processor having a normal execution mode and an isolated execution mode generates an access transaction. The access transaction is configured using a configuration storage that contains configuration settings related to a page and access information. An access checking circuit coupled to the configuration settings and the access information and generates an access grant signal if the access transaction is valid.

Abstract translation: 本发明提供一种用于控制对隔离执行环境中的多个隔离存储器区域的存储器访问的方法，装置和系统。 页面管理器用于分别将多个页面分发到存储器的多个不同区域。 记忆分为非隔离区和隔离区。 页面管理器位于隔离区内。 此外，存储器所有权页表描述了存储器的每一页，并且还位于存储器的隔离区域中。 页面管理器将分离的属性分配给页面，如果页面分发到隔离的内存。 另一方面，如果页面被分发到存储器的非隔离区域，则页面管理器将非隔离属性分配给页面。 内存所有权页表记录每个页面的属性。 在一个实施例中，具有正常执行模式和隔离执行模式的处理器生成访问事务。 访问事务使用包含与页面和访问信息相关的配置设置的配置存储进行配置。 访问检查电路，其耦合到配置设置和访问信息，并且如果访问事务有效则生成访问许可信号。

公开(公告)号：DE10196440T5

公开(公告)日：2004-04-29

申请号：DE10196440

申请日：2001-07-13

Applicant: INTEL CORP

Inventor： GOLLIVER ROGER ,  SUTTON II JAMES ,  LIN DERRICK ,  THAKKAR SHREEKANT ,  NEIGER GILBERT ,  MCKEEN FRANCIS ,  HERBERT HOWARD ,  RENERIS KENNETH ,  ELLISON CARL

IPC: G06F12/14 ,  G06F1/00

公开(公告)号：EP0868689A4

公开(公告)日：2000-02-16

申请号：EP96944983

申请日：1996-12-17

Applicant: INTEL CORP

Inventor： LIN DERRICK ,  VAKKALAGADDA RAMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI EIICHI ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, processor is provided that includes a decode unit (1002), a mapping unit (1004), and a storage unit (1006). The decode unit (1002) is configured to decode instructions and their operands from at least one instruction set including at least a first and second set of instructions. The storage unit (1006) includes a physical register file (1020). The mapping unit (1004) is configured to map operands used by the first set of instructions to the physical register file in a stock referenced manner. In addition, the mapping unit (1004) is configured to map operands used by the second set of instructions to the same physical register file in a non-stack reference manner.

Abstract translation: 一种用于执行浮点和紧缩数据说明，用一个单一的物理寄存器文件的方法和装置也被混叠。 。根据本发明的一个方面，提供了一种处理器做包括一解码单元，映射单元，以及存储单元。 解码单元被配置为指令和其操作数从至少一个指令集包括至少一个第一和第二组指令进行解码。 所述存储单元包括一个物理寄存器文件。 所述映射单元被配置为在一个股票引用方式使用由第一组的说明将物理寄存器文件的操作数。 另外，映射单元被配置成映射在一个非堆叠参考方式使用由所述第二组指令到相同的物理寄存器堆的操作数。

公开(公告)号：GB2381626A

公开(公告)日：2003-05-07

申请号：GB0303644

申请日：2001-07-13

Applicant: INTEL CORP

Inventor： GOLLIVER ROGER A ,  SUTTON JAMES II ,  LIN DERRICK ,  THAKKAR SHREEKANT ,  NEIGER GILBERT ,  MCKEEN FRANCIS ,  HERBERT HOWARD ,  RENERIS KENNETH ,  ELLISON CARL

IPC: G06F12/14

Abstract: The present invention provides a method, apparatus, and system for controlling memory accesses to multiple isolated memory areas in an isolated execution environment. A page manager is used to distribute a plurality of pages to a plurality of different areas of a memory, respectively. The memory is divided into non-isolated areas and isolated areas. The page manager is located in an isolated area of memory. Further, a memory ownership page table describes each page of memory and is also located in an isolated area of memory. The page manager assigns an isolated attribute to a page if the page is distributed to an isolated are of memory. On the other hand, the page manager assigns a non-isolated attribute to a page if the page is distributed to a non-isolated area of memory. The memory ownership page table records the attribute for each page. In one embodiment, a processor having a normal execution mode and an isolated execution mode generates an access transaction. The access transaction is configured using a configuration storage that contains configuration settings related to a page and access information. An access checking circuit coupled to the configuration settings and the access information and generates an access grant signal if the access transaction is valid.

公开(公告)号：AU7199601A

公开(公告)日：2002-01-30

申请号：AU7199601

申请日：2001-07-13

Applicant: INTEL CORP

Inventor： GOLLIVER ROGER ,  SUTTON JAMES II ,  LIN DERRICK ,  THAKKAR SHREEKANT ,  NEIGER GILBERT ,  MCKEEN FRANCIS ,  HERBERT HOWARD ,  RENERIS KENNETH ,  ELLISON CARL

IPC: G06F12/14 ,  G06F1/00

公开(公告)号：BR9612189A

公开(公告)日：1999-07-13

申请号：BR9612189

申请日：1996-12-17

Applicant: INTEL CORP

Inventor： LIN DERRICK ,  VAKKALAGADDA RAMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI EIICHI ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48 ,  G06F9/00

公开(公告)号：HK1016711A1

公开(公告)日：1999-11-05

申请号：HK99101457

申请日：1999-04-09

Applicant: INTEL CORP

Inventor： GLEW ANDREW F ,  VAKKALAGADDA RAMAMOHAN R ,  LIN DERRICK ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI EIICHI ,  EITAN BENNY

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/455 ,  G06F9/46 ,  G06F

Abstract: A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file. Furthermore, the data processing apparatus alters all tags in a set of tags corresponding to the single logical register file to a non-empty state sometime between starting the execution of the first set of instructions and completing the execution of the first instruction. The tags identifying whether registers in the single logical register file are empty or non-empty.