公开(公告)号：AU689201B2

公开(公告)日：1998-03-26

申请号：AU1516195

申请日：1994-12-21

Applicant: INTEL CORP

Inventor： NIZAR P K ,  CARSON DAVID G ,  GOLBERT ADI ,  FINZI DAVID ,  HOCHBERG YOAV

IPC: G06F13/26 ,  G06F15/17 ,  G06F9/46

Abstract: A multiprocessor programmable interrupt controller (MPIC) system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt-related messages. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus for broadcasting of I/O-generated interrupt request messages. Each processor chip has an on-board interrupt acceptance unit (IAU) that can accept interrupt requests from the interrupt bus and can broadcast on the interrupt bus interrupt request messages generated by its associated processor. Each processor can request to read the contents of the IAU control registers that are associated with another target processor. In that case, a remote read request message is generated by the IAU of the local processor and responded to, without software intervention, by the IAU of the target processor. A remote read status field indicates to the local processor the status of the data contained in a remote read register. The remote IAU is expected to respond in a fixed number of interrupt bus cycles. If the remote agent is unable to do so, then the remote read status field becomes "Invalid." If successful, the remote read status resolves to "Valid." The processor polls this field to determine the completion and success of the remote read request. Remote read requests are always successful (although the data may be valid or invalid) in that they are never retried. Remote read requests are primarily a debug feature, and a "hung" remote IAU that is unable to respond to a remote read request should not cause the debugging software to hang on the local processor.

公开(公告)号：DE69429279T2

公开(公告)日：2002-07-25

申请号：DE69429279

申请日：1994-12-21

Applicant: INTEL CORP

Inventor： NIZAR K ,  CARSON G ,  GOLBERT ADI ,  FINZI DAVID ,  HOCHBERG YOAV

IPC: G06F13/26 ,  G06F15/17 ,  G06F9/46

Abstract: A multiprocessor programmable interrupt controller (MPIC) system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt-related messages. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus for broadcasting of I/O-generated interrupt request messages. Each processor chip has an on-board interrupt acceptance unit (IAU) that can accept interrupt requests from the interrupt bus and can broadcast on the interrupt bus interrupt request messages generated by its associated processor. Each processor can request to read the contents of the IAU control registers that are associated with another target processor. In that case, a remote read request message is generated by the IAU of the local processor and responded to, without software intervention, by the IAU of the target processor. A remote read status field indicates to the local processor the status of the data contained in a remote read register. The remote IAU is expected to respond in a fixed number of interrupt bus cycles. If the remote agent is unable to do so, then the remote read status field becomes "Invalid." If successful, the remote read status resolves to "Valid." The processor polls this field to determine the completion and success of the remote read request. Remote read requests are always successful (although the data may be valid or invalid) in that they are never retried. Remote read requests are primarily a debug feature, and a "hung" remote IAU that is unable to respond to a remote read request should not cause the debugging software to hang on the local processor.

公开(公告)号：AU1516195A

公开(公告)日：1995-07-17

申请号：AU1516195

申请日：1994-12-21

Applicant: INTEL CORP

Inventor： NIZAR P K ,  CARSON DAVID G ,  GOLBERT ADI ,  FINZI DAVID ,  HOCHBERG YOAV

IPC: G06F13/26 ,  G06F15/17 ,  G06F9/46

Abstract: A multiprocessor programmable interrupt controller (MPIC) system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt-related messages. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus for broadcasting of I/O-generated interrupt request messages. Each processor chip has an on-board interrupt acceptance unit (IAU) that can accept interrupt requests from the interrupt bus and can broadcast on the interrupt bus interrupt request messages generated by its associated processor. Each processor can request to read the contents of the IAU control registers that are associated with another target processor. In that case, a remote read request message is generated by the IAU of the local processor and responded to, without software intervention, by the IAU of the target processor. A remote read status field indicates to the local processor the status of the data contained in a remote read register. The remote IAU is expected to respond in a fixed number of interrupt bus cycles. If the remote agent is unable to do so, then the remote read status field becomes "Invalid." If successful, the remote read status resolves to "Valid." The processor polls this field to determine the completion and success of the remote read request. Remote read requests are always successful (although the data may be valid or invalid) in that they are never retried. Remote read requests are primarily a debug feature, and a "hung" remote IAU that is unable to respond to a remote read request should not cause the debugging software to hang on the local processor.

公开(公告)号：GB2278214B

公开(公告)日：1998-02-25

申请号：GB9408238

申请日：1994-04-26

Applicant: INTEL CORP

Inventor： GOLBERT ADALBERTO ,  CARMEAN DOUGLAS M ,  FERNANDO ROSHAN J ,  GHORI AMAR A ,  HOCHBERG YOAV ,  KRICK ROBERT F ,  MITTAL MILIND ,  SAH ANURAG

IPC: G06F15/177 ,  G06F9/38 ,  G06F13/40 ,  G06F15/167 ,  G06F15/16

Abstract: A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system. Therefore, an inexpensive method and apparatus are provided for greatly enhancing the speed of a uniprocessing system to that of a multiprocessing system without the cost traditionally associated with multiprocessing systems.

公开(公告)号：DE4417068A1

公开(公告)日：1995-01-12

申请号：DE4417068

申请日：1994-05-14

Applicant: INTEL CORP

Inventor： GOLBERT ADALBERTO ,  CARMEAN DOUGLAS M ,  FERNANDO ROSHAN J ,  GHORI AMAR A ,  HOCHBERG YOAV ,  KRICK ROBERT F ,  MITTAL MILIND ,  SAH ANURAG

IPC: G06F15/177 ,  G06F9/38 ,  G06F13/40 ,  G06F15/167 ,  G06F15/16 ,  G06F13/24 ,  G06F12/08

Abstract: A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system. Therefore, an inexpensive method and apparatus are provided for greatly enhancing the speed of a uniprocessing system to that of a multiprocessing system without the cost traditionally associated with multiprocessing systems.

公开(公告)号：GB2278214A

公开(公告)日：1994-11-23

申请号：GB9408238

申请日：1994-04-26

Applicant: INTEL CORP

Inventor： GOLBERT ADALBERTO ,  CARMEAN DOUGLAS M ,  FERNANDO ROSHAN J ,  GHORI AMAR A ,  HOCHBERG YOAV ,  KRICK ROBERT F ,  MITTAL MILIND ,  SAH ANURAG

IPC: G06F15/177 ,  G06F9/38 ,  G06F13/40 ,  G06F15/167 ,  G06F15/16

Abstract: Upgrading a uniprocessor system to a multiprocessing system by inserting a second microprocessor into an upgrade socket. The system has a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system, which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system.

公开(公告)号：DE69429279D1

公开(公告)日：2002-01-10

申请号：DE69429279

申请日：1994-12-21

Applicant: INTEL CORP

Inventor： NIZAR K ,  CARSON G ,  GOLBERT ADI ,  FINZI DAVID ,  HOCHBERG YOAV

IPC: G06F13/26 ,  G06F15/17 ,  G06F9/46

Abstract: A multiprocessor programmable interrupt controller (MPIC) system has an interrupt bus, distinct from the system (memory) bus, for handling interrupt-related messages. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs) that are each coupled to the interrupt bus for broadcasting of I/O-generated interrupt request messages. Each processor chip has an on-board interrupt acceptance unit (IAU) that can accept interrupt requests from the interrupt bus and can broadcast on the interrupt bus interrupt request messages generated by its associated processor. Each processor can request to read the contents of the IAU control registers that are associated with another target processor. In that case, a remote read request message is generated by the IAU of the local processor and responded to, without software intervention, by the IAU of the target processor. A remote read status field indicates to the local processor the status of the data contained in a remote read register. The remote IAU is expected to respond in a fixed number of interrupt bus cycles. If the remote agent is unable to do so, then the remote read status field becomes "Invalid." If successful, the remote read status resolves to "Valid." The processor polls this field to determine the completion and success of the remote read request. Remote read requests are always successful (although the data may be valid or invalid) in that they are never retried. Remote read requests are primarily a debug feature, and a "hung" remote IAU that is unable to respond to a remote read request should not cause the debugging software to hang on the local processor.

公开(公告)号：CA2179397C

公开(公告)日：2001-08-21

申请号：CA2179397

申请日：1994-12-21

Applicant: INTEL CORP

Inventor： NIZAR P K ,  CARSON DAVID G ,  GOLBERT ADI ,  FINZI DAVID ,  HOCHBERG YOAV

IPC: G06F13/26 ,  G06F15/17 ,  G06F9/46

Abstract: A multiprocessor programmable inter- rupt controller (MPIC) has a distinct three- wire interrupt bus (15) with one clock wire and two data wires for handling interrupt request (IRQ) related messages. Each pro- cessor chip (114) has an on-board interrupt acceptance unit (IAU) coupled to the inter- rupt bus (15) for the acceptance of IRQs. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs 113) that are each coupled to the interrupt bus (15). A modification to the lowest prior- ity mode arbitration procedure also provides means for uniform distribution of IRQs to eligible processors. The actual servicing of the IRQs is done by means of the system bus (110). An MPIC cluster system provides means for interconnecting individual MPIC systems into an expanded interrupt controller system whenever the interrupt handling ca- pacity of individual MPIC system (cluster) is exceeded by using a cluster manager.

公开(公告)号：CA2179397A1

公开(公告)日：1995-07-06

申请号：CA2179397

申请日：1994-12-21

Applicant: INTEL CORP

Inventor： NIZAR P K ,  CARSON DAVID G ,  GOLBERT ADI ,  FINZI DAVID ,  HOCHBERG YOAV

IPC: G06F13/26 ,  G06F15/17 ,  G06F9/46

Abstract: A multiprocessor programmable inter- rupt controller (MPIC) has a distinct three- wire interrupt bus (15) with one clock wire and two data wires for handling interrupt request (IRQ) related messages. Each pro- cessor chip (114) has an on-board interrupt acceptance unit (IAU) coupled to the inter- rupt bus (15) for the acceptance of IRQs. I/O device interrupt lines are connected to one or more interrupt delivery units (IDUs 113) that are each coupled to the interrupt bus (15). A modification to the lowest prior- ity mode arbitration procedure also provides means for uniform distribution of IRQs to eligible processors. The actual servicing of the IRQs is done by means of the system bus (110). An MPIC cluster system provides means for interconnecting individual MPIC systems into an expanded interrupt controller system whenever the interrupt handling ca- pacity of individual MPIC system (cluster) is exceeded by using a cluster manager.

公开(公告)号：EP2974113A4

公开(公告)日：2016-12-07

申请号：EP14774500

申请日：2014-03-12

Applicant: INTEL CORP

Inventor： HOCHBERG YOAV ,  ANDERSON GLEN ,  BEN HAIM GUY ,  SMITH CHARLES ,  JOHNSON BRIAN

IPC: H04L9/00 ,  G06F21/62 ,  H04L29/06

CPC classification number: H04L63/04 ,  G06F21/6245 ,  G06F2221/2143 ,  H04L63/08 ,  H04L63/083 ,  H04L63/105 ,  H04L63/1408 ,  H04W12/06