公开(公告)号：GB2278214B

公开(公告)日：1998-02-25

申请号：GB9408238

申请日：1994-04-26

Applicant: INTEL CORP

Inventor： GOLBERT ADALBERTO ,  CARMEAN DOUGLAS M ,  FERNANDO ROSHAN J ,  GHORI AMAR A ,  HOCHBERG YOAV ,  KRICK ROBERT F ,  MITTAL MILIND ,  SAH ANURAG

IPC: G06F15/177 ,  G06F9/38 ,  G06F13/40 ,  G06F15/167 ,  G06F15/16

Abstract: A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system. Therefore, an inexpensive method and apparatus are provided for greatly enhancing the speed of a uniprocessing system to that of a multiprocessing system without the cost traditionally associated with multiprocessing systems.

公开(公告)号：DE4218003C2

公开(公告)日：1997-08-21

申请号：DE4218003

申请日：1992-06-01

Applicant: INTEL CORP

Inventor： MACWILLIAMS PETER D ,  FARRELL ROBERT L ,  GOLBERT ADALBERTO ,  SILAS ITZIK

IPC: G06F12/08

Abstract: A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus and to the main memory bus providing independent access by both buses, thereby reducing traffic of the main memory bus when the data required by the CPU is located in secondary cache. Similarly, CPU bus traffic is minimized when secondary cache access by the main memory bus for snoops and write-backs to main memory. Snoop latches interfaced with the main memory bus provide snoop access to the cache memory via the cache directory in the secondary cache controller unit. The controller also supports parallel look-up in the controller tag array and the secondary cache using most-recently-used (MRU) main memory write-through and pipelining of memory bus cycle requests.

公开(公告)号：DE4417068A1

公开(公告)日：1995-01-12

申请号：DE4417068

申请日：1994-05-14

Applicant: INTEL CORP

Inventor： GOLBERT ADALBERTO ,  CARMEAN DOUGLAS M ,  FERNANDO ROSHAN J ,  GHORI AMAR A ,  HOCHBERG YOAV ,  KRICK ROBERT F ,  MITTAL MILIND ,  SAH ANURAG

IPC: G06F15/177 ,  G06F9/38 ,  G06F13/40 ,  G06F15/167 ,  G06F15/16 ,  G06F13/24 ,  G06F12/08

Abstract: A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system. Therefore, an inexpensive method and apparatus are provided for greatly enhancing the speed of a uniprocessing system to that of a multiprocessing system without the cost traditionally associated with multiprocessing systems.

公开(公告)号：GB2278214A

公开(公告)日：1994-11-23

申请号：GB9408238

申请日：1994-04-26

Applicant: INTEL CORP

Inventor： GOLBERT ADALBERTO ,  CARMEAN DOUGLAS M ,  FERNANDO ROSHAN J ,  GHORI AMAR A ,  HOCHBERG YOAV ,  KRICK ROBERT F ,  MITTAL MILIND ,  SAH ANURAG

IPC: G06F15/177 ,  G06F9/38 ,  G06F13/40 ,  G06F15/167 ,  G06F15/16

Abstract: Upgrading a uniprocessor system to a multiprocessing system by inserting a second microprocessor into an upgrade socket. The system has a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system, which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system.

公开(公告)号：SG50468A1

公开(公告)日：1998-07-20

申请号：SG1996002169

申请日：1994-07-20

Applicant: INTEL CORP

Inventor： GHORI AMAR A ,  GOLBERT ADALBERTO ,  KRICK ROBERT F

IPC: G06F13/14 ,  G06F9/38 ,  G06F9/445 ,  G06F13/38 ,  G06F15/177 ,  G06F15/16

公开(公告)号：DE4218003A1

公开(公告)日：1992-12-10

申请号：DE4218003

申请日：1992-06-01

Applicant: INTEL CORP

Inventor： MACWILLIAMS PETER D ,  FARRELL ROBERT L ,  GOLBERT ADALBERTO ,  SILAS ITZIK

IPC: G06F12/08

Abstract: A second level cache memory system for use with a CPU having a first level cache, comprising a cache read/write memory, memory bus controller, and cache controller. Preferred embodiments of the cache controller provide for snooping as a means for maintaining data consistency in a multiprocessor system, concurrent operation of CPU and memory busses, parallel look-up in controller tag array and data array using most-recently-used way prediction for reads, CPU/main-memory write-through capability and pipelining of memory bus cycle requests.

公开(公告)号：GB2256512A

公开(公告)日：1992-12-09

申请号：GB9208138

申请日：1992-04-13

Applicant: INTEL CORP

Inventor： MACWILLIAMS PETER DALTON ,  FARRELL ROBERT L ,  GOLBERT ADALBERTO ,  SILAS ITZIK

IPC: G06F12/08

Abstract: A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus and to the main memory bus providing independent access by both buses, thereby reducing traffic of the main memory bus when the data required by the CPU is located in secondary cache. Similarly, CPU bus traffic is minimized when secondary cache access by the main memory bus for snoops and write-backs to main memory. Snoop latches interfaced with the main memory bus provide snoop access to the cache memory via the cache directory in the secondary cache controller unit. The controller also supports parallel look-up in the controller tag array and the secondary cache using most-recently-used (MRU) main memory write-through and pipelining of memory bus cycle requests.

公开(公告)号：SG47048A1

公开(公告)日：1998-03-20

申请号：SG1996004256

申请日：1994-04-26

Applicant: INTEL CORP

Inventor： GOLBERT ADALBERTO ,  CARMEAN DOUGLAS M ,  FERNANDO ROSHAN J ,  GHORI AMAR A ,  HOCHBERG YOAV ,  KRICK ROBERT F ,  MITTAL MILIND ,  SAH ANURAG

IPC: G06F15/177 ,  G06F9/38 ,  G06F13/40 ,  G06F15/167 ,  G06F15/16

Abstract: A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system. Therefore, an inexpensive method and apparatus are provided for greatly enhancing the speed of a uniprocessing system to that of a multiprocessing system without the cost traditionally associated with multiprocessing systems.

公开(公告)号：FR2677472B1

公开(公告)日：1997-04-18

申请号：FR9206641

申请日：1992-06-02

Applicant: INTEL CORP

Inventor： MACWILLIAMS PETER D ,  FARRELL ROBERT L ,  GOLBERT ADALBERTO ,  SILAS ITZIK

IPC: G06F12/08 ,  G06F13/14 ,  G06F12/00 ,  G06F13/16

Abstract: A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus and to the main memory bus providing independent access by both buses, thereby reducing traffic of the main memory bus when the data required by the CPU is located in secondary cache. Similarly, CPU bus traffic is minimized when secondary cache access by the main memory bus for snoops and write-backs to main memory. Snoop latches interfaced with the main memory bus provide snoop access to the cache memory via the cache directory in the secondary cache controller unit. The controller also supports parallel look-up in the controller tag array and the secondary cache using most-recently-used (MRU) main memory write-through and pipelining of memory bus cycle requests.

公开(公告)号：HK153995A

公开(公告)日：1995-10-06

申请号：HK153995

申请日：1995-09-28

Applicant: INTEL CORP

Inventor： MCWILLIAMS PETER DALTON ,  FARRELL ROBERT L ,  GOLBERT ADALBERTO ,  SILAS ITZIK

IPC: G06F12/08

Abstract: A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus and to the main memory bus providing independent access by both buses, thereby reducing traffic of the main memory bus when the data required by the CPU is located in secondary cache. Similarly, CPU bus traffic is minimized when secondary cache access by the main memory bus for snoops and write-backs to main memory. Snoop latches interfaced with the main memory bus provide snoop access to the cache memory via the cache directory in the secondary cache controller unit. The controller also supports parallel look-up in the controller tag array and the secondary cache using most-recently-used (MRU) main memory write-through and pipelining of memory bus cycle requests.