公开(公告)号：SG47048A1

公开(公告)日：1998-03-20

申请号：SG1996004256

申请日：1994-04-26

Applicant: INTEL CORP

Inventor： GOLBERT ADALBERTO ,  CARMEAN DOUGLAS M ,  FERNANDO ROSHAN J ,  GHORI AMAR A ,  HOCHBERG YOAV ,  KRICK ROBERT F ,  MITTAL MILIND ,  SAH ANURAG

IPC: G06F15/177 ,  G06F9/38 ,  G06F13/40 ,  G06F15/167 ,  G06F15/16

Abstract: A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system. Therefore, an inexpensive method and apparatus are provided for greatly enhancing the speed of a uniprocessing system to that of a multiprocessing system without the cost traditionally associated with multiprocessing systems.

公开(公告)号：GB2278214B

公开(公告)日：1998-02-25

申请号：GB9408238

申请日：1994-04-26

Applicant: INTEL CORP

Inventor： GOLBERT ADALBERTO ,  CARMEAN DOUGLAS M ,  FERNANDO ROSHAN J ,  GHORI AMAR A ,  HOCHBERG YOAV ,  KRICK ROBERT F ,  MITTAL MILIND ,  SAH ANURAG

IPC: G06F15/177 ,  G06F9/38 ,  G06F13/40 ,  G06F15/167 ,  G06F15/16

Abstract: A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system. Therefore, an inexpensive method and apparatus are provided for greatly enhancing the speed of a uniprocessing system to that of a multiprocessing system without the cost traditionally associated with multiprocessing systems.

公开(公告)号：DE4417068A1

公开(公告)日：1995-01-12

申请号：DE4417068

申请日：1994-05-14

Applicant: INTEL CORP

Inventor： GOLBERT ADALBERTO ,  CARMEAN DOUGLAS M ,  FERNANDO ROSHAN J ,  GHORI AMAR A ,  HOCHBERG YOAV ,  KRICK ROBERT F ,  MITTAL MILIND ,  SAH ANURAG

IPC: G06F15/177 ,  G06F9/38 ,  G06F13/40 ,  G06F15/167 ,  G06F15/16 ,  G06F13/24 ,  G06F12/08

Abstract: A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system. Therefore, an inexpensive method and apparatus are provided for greatly enhancing the speed of a uniprocessing system to that of a multiprocessing system without the cost traditionally associated with multiprocessing systems.

公开(公告)号：GB2278214A

公开(公告)日：1994-11-23

申请号：GB9408238

申请日：1994-04-26

Applicant: INTEL CORP

Inventor： GOLBERT ADALBERTO ,  CARMEAN DOUGLAS M ,  FERNANDO ROSHAN J ,  GHORI AMAR A ,  HOCHBERG YOAV ,  KRICK ROBERT F ,  MITTAL MILIND ,  SAH ANURAG

IPC: G06F15/177 ,  G06F9/38 ,  G06F13/40 ,  G06F15/167 ,  G06F15/16

Abstract: Upgrading a uniprocessor system to a multiprocessing system by inserting a second microprocessor into an upgrade socket. The system has a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system, which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system.