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    RESCHEDULING MULTIPLE MICRO-OPERATIONS IN A PROCESSOR USING A REPLAY QUEUE
    1.
    发明申请
    RESCHEDULING MULTIPLE MICRO-OPERATIONS IN A PROCESSOR USING A REPLAY QUEUE 审中-公开
    使用REPLAY QUEUE对处理器中的多个微操作进行排序

    公开(公告)号：WO0242902A2

    公开(公告)日：2002-05-30

    申请号：PCT/US0151023

    申请日：2001-10-18

    Applicant: INTEL CORP ,  CARMEAN DOUGLAS M ,  BOGGS DARRELL D ,  SAGER DAVID J ,  MCKEEN FRANCIS X ,  HAMMARLUND PER ,  SINGHAL RONAK

    Inventor： CARMEAN DOUGLAS M ,  BOGGS DARRELL D ,  SAGER DAVID J ,  MCKEEN FRANCIS X ,  HAMMARLUND PER ,  SINGHAL RONAK

    IPC: G06F9/38 ,  G06F9/00

    CPC classification number: G06F9/3842 ,  G06F9/3861

    Abstract: Rescheduling multiple micro-operations in a processor using a replay queue. The processor comprises a replay queue to receive a plurality of instructions and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and dispatches each instruction to the execution unit. A checker is couple to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

    Abstract translation: 使用重放队列在处理器中重新安排多个微操作。 处理器包括用于接收多个指令的重放队列和执行多个指令的执行单元。 调度器耦合在重播队列和执行单元之间。 调度器推测性地安排执行指令并将每个指令分派到执行单元。 检查器耦合到执行单元，以确定每个指令是否已成功执行。 检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

    APPARATUS AND METHOD TO RESCHEDULE INSTRUCTIONS
    2.
    发明申请
    APPARATUS AND METHOD TO RESCHEDULE INSTRUCTIONS 审中-公开
    装置说明书和方法

    公开(公告)号：WO0239269A3

    公开(公告)日：2003-01-23

    申请号：PCT/US0150735

    申请日：2001-10-18

    Applicant: INTEL CORP ,  CARMEAN DOUGLAS M ,  BOGGS DARRELL D ,  SAGER DAVID J ,  MCKEEN FRANCIS X ,  HAMMARLUND PER ,  SINGHAL RONAK

    Inventor： CARMEAN DOUGLAS M ,  BOGGS DARRELL D ,  SAGER DAVID J ,  MCKEEN FRANCIS X ,  HAMMARLUND PER ,  SINGHAL RONAK

    IPC: G06F9/38

    CPC classification number: G06F9/3842 ,  G06F9/3861

    Abstract: Breaking replay dependency loops in a processor using a rescheduled replay queue. The processor comprise a replay queue to receive a plurality of instructions, and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and increments a counter for each of the plurality of instructions to reflect the number of times each of the plurality of instructions has been executed. The scheduler also dispatches each instruction to the execution unit either when the counter does not exceed a maximum number of replays or, if the counter exceeds the maximum number of replays, when the instruction is safe to execute. A checker is coupled tot he execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

    Abstract translation: 使用重新安排的重播队列在处理器中重新播放依赖循环。 处理器包括用于接收多个指令的重播队列，以及执行多个指令的执行单元。 调度器耦合在重播队列和执行单元之间。 调度器推测性地调度用于执行的指令，并且为多个指令中的每一个递增计数器，以反映多个指令中的每一个已被执行的次数。 当计数器不超过最大重放次数时，或者当计数器超过最大重放次数时，当指令执行安全时，调度器也将每条指令分派给执行单元。 检查器与执行单元相连以确定每个指令是否已成功执行。 检查器还耦合到重播队列，以便与未执行成功的每个指令通信给重播队列。

    A cache coherent multiprocessing computer system with reduced power operating features.
    4.
    发明专利
    A cache coherent multiprocessing computer system with reduced power operating features. 未知

    公开(公告)号：HK1003667A1

    公开(公告)日：1998-11-06

    申请号：HK98102962

    申请日：1998-04-08

    Applicant: INTEL CORP

    Inventor： CARMEAN DOUGLAS M ,  CRAWFORD JOHN

    IPC: G06F15/00 ,  G06F1/32 ,  G06F9/30 ,  G06F12/08 ,  G06F

    Abstract: A multiprocessing system maintains cache coherency during a reduced power mode of operation. The multiprocessing system has a first and a second processor coupled to the bus to perform data transactions with the main memory. During the reduced power mode of operation, the internal clock signal of the second processor is decoupled from a portion of the internal logic of the second processor while remaining coupled to a portion of the internal logic of the second processor that is used to monitor and respond to the traffic on the external bus to maintain cache coherency. During the reduced power mode of operation, the second processor continues to perform snoop and write-back processes to maintain a cache coherent multiprocessing system.

    A cache coherent multiprocessing computer system with reduce d power operating features
    7.
    发明专利
    A cache coherent multiprocessing computer system with reduce d power operating features 未知

    公开(公告)号：AU4962196A

    公开(公告)日：1996-10-30

    申请号：AU4962196

    申请日：1995-12-20

    Applicant: INTEL CORP

    Inventor： CARMEAN DOUGLAS M ,  CRAWFORD JOHN

    IPC: G06F15/00 ,  G06F1/32 ,  G06F9/30 ,  G06F12/08 ,  G06F12/00 ,  G06F13/00

    Abstract: A multiprocessing system maintains cache coherency during a reduced power mode of operation. The multiprocessing system has a first and a second processor coupled to the bus to perform data transactions with the main memory. During the reduced power mode of operation, the internal clock signal of the second processor is decoupled from a portion of the internal logic of the second processor while remaining coupled to a portion of the internal logic of the second processor that is used to monitor and respond to the traffic on the external bus to maintain cache coherency. During the reduced power mode of operation, the second processor continues to perform snoop and write-back processes to maintain a cache coherent multiprocessing system.

    Rescheduling multiple micro-operations in a processor using replay queue
    9.
    发明专利
    Rescheduling multiple micro-operations in a processor using replay queue 未知

    公开(公告)号：AU3135802A

    公开(公告)日：2002-06-03

    申请号：AU3135802

    申请日：2001-10-18

    Applicant: INTEL CORP

    Inventor： CARMEAN DOUGLAS M ,  BOGGS DARRELL D ,  SAGER DAVID J ,  MCKEEN FRANCIS X ,  HAMMARLUND PER ,  SINGHAL RONAK

    IPC: G06F9/38 ,  G06F9/00

    Abstract: Rescheduling multiple micro-operations in a processor using a replay queue. The processor comprises a replay queue to receive a plurality of instructions and an execution unit to execute the plurality of instructions. A scheduler is coupled between the replay queue and the execution unit. The scheduler speculatively schedules instructions for execution and dispatches each instruction to the execution unit. A checker is coupled to the execution unit to determine whether each instruction has executed successfully. The checker is also coupled to the replay queue to communicate to the replay queue each instruction that has not executed successfully.

    Method and apparatus for maintaining processor ordering
    10.
    发明专利
    Method and apparatus for maintaining processor ordering 未知

    公开(公告)号：AU1787801A

    公开(公告)日：2001-07-16

    申请号：AU1787801

    申请日：2000-11-21

    Applicant: INTEL CORP

    Inventor： CHOWDHURY MUNTAQUIM E ,  CARMEAN DOUGLAS M

    IPC: G06F9/38

    Abstract: An apparatus in a first processor includes a first data structure to store addresses of store instruction dispatched during a last predetermined number of cycles. The apparatus further includes logic to determine whether a load address of a load instruction being executed matches one of the store addresses in the first data structure. The apparatus still further includes logic to replay to the respective load instruction if the load address of the respective load instruction matches of the store addresses in the first data structure.

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