公开(公告)号：BR9509841A

公开(公告)日：1997-11-25

申请号：BR9509841

申请日：1995-12-01

Applicant: INTEL CORP

Inventor： PELEG ALEXANDER ,  YAARI YAAKOV ,  MITTAL MILIND ,  MENNEMEIER LARRY M ,  EITAN BENNY

IPC: G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  G06F9/30 ,  G06F9/315 ,  G06F9/38

Abstract: A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.

公开(公告)号：GB2326494A

公开(公告)日：1998-12-23

申请号：GB9811430

申请日：1996-12-17

Applicant: INTEL CORP

Inventor： GLEW ANDREW F ,  VAKKALAGADDA RAMAMOHAN R ,  LIN DERRICK ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER ,  BISTRY DAVID ,  MITTAL MILIND ,  DULONG CAROLE ,  KOWASHI EIICHI ,  EITAN BENNY

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/455 ,  G06F9/46 ,  G06F9/34 ,  G06F9/00 ,  G06F9/302

Abstract: A method for executing different sets of instructions that cause a processor (505) to perform different data type operations in a manner that is invisible to various operating system techniques. According to one embodiment of the invention, a data processing apparatus (505) executes both a first set of instructions of a first data type and a first instruction of a second data type using one or more physical register files that at least appear to software as a single logical register file (300, 310). While executing the first set of instructions, the single logical register file (300,310) is operated as a flat register file. While executing the first instruction of the second data type, the single logical register file (300, 310) is operated as a stack referenced (340) register file. Furthermore, the data processing apparatus alters all tags in a set of tags (320, 330) corresponding to the single logical register file (300, 310) to a non-empty state sometime between starting the execution of the first set of instructions and completing the execution of the first instruction.

公开(公告)号：SG47048A1

公开(公告)日：1998-03-20

申请号：SG1996004256

申请日：1994-04-26

Applicant: INTEL CORP

Inventor： GOLBERT ADALBERTO ,  CARMEAN DOUGLAS M ,  FERNANDO ROSHAN J ,  GHORI AMAR A ,  HOCHBERG YOAV ,  KRICK ROBERT F ,  MITTAL MILIND ,  SAH ANURAG

IPC: G06F15/177 ,  G06F9/38 ,  G06F13/40 ,  G06F15/167 ,  G06F15/16

Abstract: A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system. Therefore, an inexpensive method and apparatus are provided for greatly enhancing the speed of a uniprocessing system to that of a multiprocessing system without the cost traditionally associated with multiprocessing systems.

公开(公告)号：BR9509845A

公开(公告)日：1997-12-30

申请号：BR9509845

申请日：1995-12-01

Applicant: INTEL CORP

Inventor： PELEG ALEXANDER ,  YAARI YAAKOW ,  MITTAL MILIND ,  MENNEMEIR LARRY M ,  EITAN BENNY

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F9/318 ,  G06F7/14

Abstract: A processor includes a first register (209) for storing a first packed data, a decoder (202), and a functional unit (203). The decoder has a control signal input (207) for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation, and the second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder (202) and the register (209). The functional unit performs the pack operation and the unpack operation using the first packed data as well as move operation.

公开(公告)号：GB2326494B

公开(公告)日：2000-08-23

申请号：GB9811430

申请日：1996-12-17

Applicant: INTEL CORP

Inventor： GLEW ANDREW F ,  VAKKALAGADDA RAMAMOHAN R ,  LIN DERRICK ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER ,  BISTRY DAVID ,  MITTAL MILIND ,  DULONG CAROLE ,  KOWASHI EIICHI ,  EITAN BENNY

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/455 ,  G06F9/46 ,  G06F9/34 ,  G06F9/00 ,  G06F9/302

Abstract: A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file. Furthermore, the data processing apparatus alters all tags in a set of tags corresponding to the single logical register file to a non-empty state sometime between starting the execution of the first set of instructions and completing the execution of the first instruction. The tags identifying whether registers in the single logical register file are empty or non-empty.

公开(公告)号：GB2278214B

公开(公告)日：1998-02-25

申请号：GB9408238

申请日：1994-04-26

Applicant: INTEL CORP

Inventor： GOLBERT ADALBERTO ,  CARMEAN DOUGLAS M ,  FERNANDO ROSHAN J ,  GHORI AMAR A ,  HOCHBERG YOAV ,  KRICK ROBERT F ,  MITTAL MILIND ,  SAH ANURAG

IPC: G06F15/177 ,  G06F9/38 ,  G06F13/40 ,  G06F15/167 ,  G06F15/16

Abstract: A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system. Therefore, an inexpensive method and apparatus are provided for greatly enhancing the speed of a uniprocessing system to that of a multiprocessing system without the cost traditionally associated with multiprocessing systems.

公开(公告)号：DE4417068A1

公开(公告)日：1995-01-12

申请号：DE4417068

申请日：1994-05-14

Applicant: INTEL CORP

Inventor： GOLBERT ADALBERTO ,  CARMEAN DOUGLAS M ,  FERNANDO ROSHAN J ,  GHORI AMAR A ,  HOCHBERG YOAV ,  KRICK ROBERT F ,  MITTAL MILIND ,  SAH ANURAG

IPC: G06F15/177 ,  G06F9/38 ,  G06F13/40 ,  G06F15/167 ,  G06F15/16 ,  G06F13/24 ,  G06F12/08

Abstract: A method and apparatus for upgrading a uniprocessor system to a multiprocessing system simply by the insertion of a second microprocessor integrated circuit. The computer system is provided with an upgrade socket for receiving the second processing unit, as well as a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system. Therefore, an inexpensive method and apparatus are provided for greatly enhancing the speed of a uniprocessing system to that of a multiprocessing system without the cost traditionally associated with multiprocessing systems.

公开(公告)号：GB2278214A

公开(公告)日：1994-11-23

申请号：GB9408238

申请日：1994-04-26

Applicant: INTEL CORP

Inventor： GOLBERT ADALBERTO ,  CARMEAN DOUGLAS M ,  FERNANDO ROSHAN J ,  GHORI AMAR A ,  HOCHBERG YOAV ,  KRICK ROBERT F ,  MITTAL MILIND ,  SAH ANURAG

IPC: G06F15/177 ,  G06F9/38 ,  G06F13/40 ,  G06F15/167 ,  G06F15/16

Abstract: Upgrading a uniprocessor system to a multiprocessing system by inserting a second microprocessor into an upgrade socket. The system has a private communications bus between the upgrade socket and the existing processor for handling interprocessor communications, bus arbitration and cache coherency, etc. The addition of the second processor is transparent to the system, which maintains its memory management unit and caching system and other arrangements as though it were still a uniprocessing system.