公开(公告)号：JP2008300877A

公开(公告)日：2008-12-11

申请号：JP2008224148

申请日：2008-09-01

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： LI JIAN ,  VU QUAT ,  TOWLE STEVEN

IPC: H01L23/12 ,  H01L25/07 ,  H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/52 ,  H01L23/538 ,  H01L25/04 ,  H01L25/18

CPC classification number: H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To develop novel substrates/circuit boards achieving faster speed and higher performance in order to provide a desirable microelectronic substrate. SOLUTION: The microelectronic substrate including at least one microelectronic die disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic dice, or a plurality of microelectronic dice encapsulated without the microelectronic substrate core. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：开发新颖的基板/电路板，实现更快的速度和更高的性能，以便提供期望的微电子基板。 解决方案：微电子衬底包括设置在微电子衬底芯中的开口内的至少一个微电子管芯，其中封装材料设置在不被微电子管芯占据的开口的部分内，或者多个微电子管芯被封装而没有 微电子衬底芯。 然后在微电子管芯，封装材料和微电子衬底芯（如果存在）上制造介电材料和导电迹线的互连层以形成微电子衬底。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：WO0221595A3

公开(公告)日：2003-08-14

申请号：PCT/US0126949

申请日：2001-08-29

Applicant: INTEL CORP

Inventor： HENAO MARIA ,  MU XIAO-CHUN ,  MA QING ,  VU QUAT ,  LI JIAN

IPC: H01L23/532 ,  H01L23/538 ,  H01L23/31

CPC classification number: H01L24/19 ,  H01L21/568 ,  H01L23/532 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/92 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  Y10T29/4935 ,  H01L2224/96 ,  H01L2224/82 ,  H01L2924/00

Abstract: A microelectronic package including a microelectronic die disposed within an opening in a microelectronic packaging core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic die. Build-up layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulant material, and the microelectronic package core to form the microelectronic package.

Abstract translation: 一种微电子封装，包括设置在微电子封装芯中的开口内的微电子管芯，其中封装材料设置在不被微电子管芯占据的开口部分内。 然后在微电子管芯，密封剂材料和微电子封装芯上制造介电材料和导电迹线的堆叠层以形成微电子封装。

公开(公告)号：WO0117013A3

公开(公告)日：2001-10-25

申请号：PCT/US0040681

申请日：2000-08-18

Applicant: INTEL CORP ,  LI JIAN ,  MU XIAO CHUN ,  BALAKRISHNAN SRIDHAR

Inventor： LI JIAN ,  MU XIAO-CHUN ,  BALAKRISHNAN SRIDHAR

IPC: H01L21/60 ,  H01L23/485 ,  H01L21/285

CPC classification number: H01L23/485 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  Y10T428/12479 ,  Y10T428/12556 ,  Y10T428/12583 ,  Y10T428/12743 ,  Y10T428/12812 ,  Y10T428/31678 ,  H01L2224/05552

Abstract: Methods and apparatuses are disclosed for forming an under bump metallizaton structure that includes a refractory hydride layer. The refractory layer is formed during rapid thermal processing wherein ambient hydrogen is used in the thermal processing chamber. Rapid thermal processing may occur at a temperature approximately in the range of 350 DEG C approximately 550 DEG C.

Abstract translation: 公开了用于形成包括耐火氢化物层的凸块下金属化结构的方法和装置。 耐火层在快速热处理期间形成，其中环境氢被用于热处理室中。 快速热处理可以在约350℃至约550℃的温度下进行。

公开(公告)号：WO0233751A3

公开(公告)日：2003-08-14

申请号：PCT/US0131438

申请日：2001-10-09

Applicant: INTEL CORP

Inventor： LI JIAN ,  VU QUAT ,  TOWLE STEVEN

IPC: H01L23/12 ,  H01L21/56 ,  H01L21/68 ,  H01L23/538 ,  H01L25/04 ,  H01L25/18

CPC classification number: H01L21/568 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/20 ,  H01L2224/24137 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/12042 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00

Abstract: A microelectronic substrate including at least one microelectronic die disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic dice, or a plurality microelectronic dice encapsulated without the microelectronic substrate core. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.

Abstract translation: 微电子衬底包括设置在微电子衬底芯中的开口内的至少一个微电子管芯，其中封装材料设置在未被微电子管芯占据的开口的部分内，或者多个微电子管芯封装而不具有微电子衬底芯。 然后在微电子管芯，封装材料和微电子衬底芯（如果存在）上制造介电材料和导电迹线的互连层以形成微电子衬底。

公开(公告)号：AT438925T

公开(公告)日：2009-08-15

申请号：AT01977612

申请日：2001-10-09

Applicant: INTEL CORP

Inventor： LI JIAN ,  VU QUAT ,  TOWLE STEVEN

IPC: H01L23/12 ,  H01L23/538 ,  H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L25/04 ,  H01L25/18 ,  H05K1/18 ,  H05K3/46

Abstract: A microelectronic substrate including at least one microelectronic die disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic dice, or a plurality microelectronic dice encapsulated without the microelectronic substrate core. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.

公开(公告)号：DE10084995B4

公开(公告)日：2008-04-03

申请号：DE10084995

申请日：2000-08-18

Applicant: INTEL CORP

Inventor： LI JIAN ,  MU XIAO-CHUN ,  BALAKRISHNAN SRIDHAR

IPC: H01L21/60 ,  H01L23/485 ,  H01L23/50

公开(公告)号：DE10296984T5

公开(公告)日：2004-10-14

申请号：DE10296984

申请日：2002-06-28

Applicant: INTEL CORP

Inventor： ISENBERGER MARK ,  MU XIAO-CHUN ,  LI JIAN

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/51 ,  G11C11/22 ,  H01L21/64

Abstract: One embodiment of the invention relates to a polymer memory device and a method of making it. The polymer memory device may include a composite or single layer of a ferroelectric polymer memory that addresses surface engineering needs according to various embodiments. The ferroelectric polymer memory structure may include crystalline ferroelectric polymer layers such as single and co-polymer compositions. The structure may include spin-on and/or Langmuir-Blodgett deposited compositions. One embodiment of the invention relates to a method making embodiments of the polymer memory device. One embodiment of the invention relates to a memory system that allows the polymer memory device to interface with various existing hosts.

公开(公告)号：AU9671901A

公开(公告)日：2002-04-29

申请号：AU9671901

申请日：2001-10-09

Applicant: INTEL CORP

Inventor： LI JIAN ,  VU QUAT ,  TOWLE STEVEN

IPC: H01L23/12 ,  H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/538 ,  H01L25/04 ,  H01L25/18 ,  H05K1/18 ,  H05K3/46

Abstract: A microelectronic substrate including at least one microelectronic die disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic dice, or a plurality microelectronic dice encapsulated without the microelectronic substrate core. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.

公开(公告)号：AU8851001A

公开(公告)日：2002-03-22

申请号：AU8851001

申请日：2001-08-29

Applicant: INTEL CORP

Inventor： HENAO MARIA ,  MU XIAO-CHUN ,  MA QING ,  VU QUAT ,  LI JIAN

IPC: H01L23/532 ,  H01L23/538

公开(公告)号：DE60139504D1

公开(公告)日：2009-09-17

申请号：DE60139504

申请日：2001-10-09

Applicant: INTEL CORP

Inventor： LI JIAN ,  VU QUAT ,  TOWLE STEVEN

IPC: H01L23/12 ,  H01L23/538 ,  H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L25/04 ,  H01L25/18 ,  H05K1/18 ,  H05K3/46

Abstract: A microelectronic substrate including at least one microelectronic die disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic dice, or a plurality microelectronic dice encapsulated without the microelectronic substrate core. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic die, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.