公开(公告)号：WO2010077842A2

公开(公告)日：2010-07-08

申请号：PCT/US2009067983

申请日：2009-12-15

Applicant: INTEL CORP ,  SHAEFFER GAD ,  RAIKIN SHLOMO ,  BASSIN VADIM ,  SADE RAANAN ,  COHEN EHUD ,  MARGULIS OLEG

Inventor： SHAEFFER GAD ,  RAIKIN SHLOMO ,  BASSIN VADIM ,  SADE RAANAN ,  COHEN EHUD ,  MARGULIS OLEG

IPC: G06F9/06 ,  G06F9/46 ,  G06F12/00

CPC classification number: G06F12/0615 ,  G06F9/467 ,  G06F12/0842 ,  G06F12/1027

Abstract: A method and apparatus for metaphysical address space for holding lossy metadata is herein described. An explicit or implicit metadata access operation referencing data address of a data item is encountered. Hardware modifies the data address to a metadata address including a metaphysical extension. The metaphysical extension overlays one or more metaphysical address space(s) on the data address space. A portion of the metadata address including the metaphysical extension is utilized to search a tag array of the cache memory holding the data item. As a result, metadata access operations only hit metadata entries of the cache based on the metadata address extension. However, as the metadata is held within the cache, the metadata potentially competes with data for space within the cache.

Abstract translation: 这里描述用于保存有损元数据的形而上学地址空间的方法和装置。 遇到引用数据项的数据地址的显式或隐式元数据访问操作。 硬件将数据地址修改为包括形而上学扩展的元数据地址。 形而上学扩展覆盖了数据地址空间上的一个或多个形而上学地址空间。 使用包括形而上学扩展的元数据地址的一部分来搜索保存数据项的高速缓冲存储器的标签阵列。 因此，元数据访问操作仅基于元数据地址扩展名来命中高速缓存的元数据条目。 然而，随着元数据被保存在高速缓存中，元数据可能与高速缓存中的空间的数据竞争。

公开(公告)号：WO2010077884A3

公开(公告)日：2010-09-30

申请号：PCT/US2009068114

申请日：2009-12-15

Applicant: INTEL CORP ,  SHEAFFER GAD ,  RAIKIN SHLOMO ,  BASSIN VADIM ,  COHEN EHUD ,  MARGULIS OLEG

Inventor： SHEAFFER GAD ,  RAIKIN SHLOMO ,  BASSIN VADIM ,  COHEN EHUD ,  MARGULIS OLEG

IPC: G06F12/08 ,  G06F9/06

CPC classification number: G06F9/3834 ,  G06F9/30076 ,  G06F9/3838 ,  G06F11/0715 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/3017 ,  G06F11/3037 ,  G06F11/3089 ,  G06F11/3471 ,  G06F12/0831 ,  G06F12/084 ,  G06F2201/885

Abstract: A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model.

Abstract translation: 这里描述了一种用于提供用于硬件属性以支持事务执行的存储器模型的方法和装置。 在遇到诸如加载读取监视器，写入监视器或缓冲属性的测试监视器操作的硬件属性的负载时，响应于指示硬件属性已经丢失的丢失字段而发出故障。 此外，基于地址依赖性和访问类型依赖性，为属性访问操作提供依赖操作，例如阻塞和转发。 因此，在存储器模型中允许和限制属性丢失和测试的不同场景。

公开(公告)号：GB2519877B

公开(公告)日：2015-07-29

申请号：GB201500492

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

IPC: G06F9/30 ,  G06F9/318 ,  G06F12/10

公开(公告)号：AU2010337318B2

公开(公告)日：2016-02-18

申请号：AU2010337318

申请日：2010-11-10

Applicant: INTEL CORP

Inventor： ADL-TABATABAI ALI-REZA ,  NI YANG ,  SAHA BRATIN ,  CALLAHAN DAVID ,  BASSIN VADIM ,  SHEAFFER GAD

IPC: G06F3/06 ,  G06F9/06 ,  G06F9/22 ,  G06F9/46

Abstract: In one embodiment, the present invention includes a method for executing a transactional memory (TM) transaction in a first thread, buffering a block of data in a first buffer of a cache memory of a processor, and acquiring a write monitor on the block to obtain ownership of the block at an encounter time in which data at a location of the block in the first buffer is updated. Other embodiments are described and claimed.

公开(公告)号：AU2010337319A1

公开(公告)日：2012-07-12

申请号：AU2010337319

申请日：2010-11-10

Applicant: INTEL CORP

Inventor： ADL-TABATABAI ALI-REZA ,  SAHA BRATIN ,  BASSIN VADIM ,  SHEAFFER GAD ,  GRAY JAN ,  GROVER VINOD ,  TAILLEFER MARTIN ,  LEVANONI YOSSI ,  DETLEFS DAVE ,  MAGRUDER MIKE ,  TOLTON MATT

IPC: G06F12/08 ,  G06F13/14

Abstract: In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.

公开(公告)号：WO2011081719A3

公开(公告)日：2011-11-24

申请号：PCT/US2010056172

申请日：2010-11-10

Applicant: INTEL CORP ,  ADL-TABATABAI ALI-REZA ,  SAHA BRATIN ,  BASSIN VADIM ,  SHEAFFER GAD ,  GRAY JAN ,  GROVER VINOD ,  TAILLEFER MARTIN ,  LEVANONI YOSSI ,  DETLEFS DAVE ,  MAGRUDER MIKE ,  TOLTON MATT

Inventor： ADL-TABATABAI ALI-REZA ,  SAHA BRATIN ,  BASSIN VADIM ,  SHEAFFER GAD ,  GRAY JAN ,  GROVER VINOD ,  TAILLEFER MARTIN ,  LEVANONI YOSSI ,  DETLEFS DAVE ,  MAGRUDER MIKE ,  TOLTON MATT

IPC: G06F13/14 ,  G06F12/08

CPC classification number: G06F12/0815 ,  G06F9/467 ,  G06F11/141

Abstract: In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于在具有多个事务执行模式的无界事务存储器（UTM）系统中选择开始第一事务的第一事务执行模式的方法。 这些事务执行模式包括在处理器的高速缓冲存储器内执行的硬件模式，使用处理器的事务硬件执行的硬件辅助模式以及软件缓冲器，以及在没有事务性硬件的情况下执行的软件事务存储器（STM）模式。 如果在STM模式下没有执行等待事务，则可以将第一事务执行模式选择为硬件模式的最高执行模式，否则可以选择较低的执行模式。 描述和要求保护其他实施例。

公开(公告)号：WO2010077885A3

公开(公告)日：2010-10-07

申请号：PCT/US2009068121

申请日：2009-12-15

Applicant: INTEL CORP ,  SHEAFFER GAD ,  RAIKIN SHLOMO ,  BASSIN VADIM ,  COHEN EHUD ,  MARGULIS OLEG ,  SADE RAANAN

Inventor： SHEAFFER GAD ,  RAIKIN SHLOMO ,  BASSIN VADIM ,  COHEN EHUD ,  MARGULIS OLEG ,  SADE RAANAN

IPC: G06F9/06 ,  G06F5/00 ,  G06F9/46 ,  G06F12/00

CPC classification number: G06F9/3834 ,  G06F9/467 ,  G06F12/0831 ,  G06F12/084

Abstract: A method and apparatus for extending cache coherency to hold buffered data to support transactional execution is herein described. A transactional store operation referencing an address associated with a data item is performed in a buffered manner. Here, the coherency state associated with cache lines to hold the data item are transitioned to a buffered state. In response to local requests for the buffered data item, the data item is provided to ensure internal transactional sequential ordering. However, in response to external access requests, a miss response is provided to ensure the transactionally updated data item is not made globally visible until commit. Upon commit, the buffered lines are transitioned to a modified state to make the data item globally visible.

Abstract translation: 这里描述了用于扩展高速缓存一致性以保存缓冲数据以支持事务执行的方法和装置。 以缓冲的方式执行引用与数据项相关联的地址的事务存储操作。 这里，与保存数据项的高速缓存行相关联的一致性状态被转换到缓冲状态。 响应缓冲数据项的本地请求，提供数据项以确保内部事务顺序排序。 然而，响应于外部访问请求，提供了错误响应以确保事务更新的数据项在提交之前不会被全局可见。 一旦提交，缓存的行将转换到修改状态，使数据项全局可见。

公开(公告)号：AU2010337319B2

公开(公告)日：2016-02-04

申请号：AU2010337319

申请日：2010-11-10

Applicant: INTEL CORP

Inventor： ADL-TABATABAI ALI-REZA ,  SAHA BRATIN ,  BASSIN VADIM ,  SHEAFFER GAD ,  GRAY JAN ,  GROVER VINOD ,  TAILLEFER MARTIN ,  LEVANONI YOSSI ,  DETLEFS DAVE ,  MAGRUDER MIKE ,  TOLTON MATT

IPC: G06F12/08 ,  G06F13/14

Abstract: In one embodiment, the present invention includes a method for selecting a first transaction execution mode to begin a first transaction in a unbounded transactional memory (UTM) system having a plurality of transaction execution modes. These transaction execution modes include hardware modes to execute within a cache memory of a processor, a hardware assisted mode to execute using transactional hardware of the processor and a software buffer, and a software transactional memory (STM) mode to execute without the transactional hardware. The first transaction execution mode can be selected to be a highest performant of the hardware modes if no pending transaction is executing in the STM mode, otherwise a lower performant mode can be selected. Other embodiments are described and claimed.

公开(公告)号：BRPI0920789A2

公开(公告)日：2015-12-22

申请号：BRPI0920789

申请日：2009-12-15

Applicant: INTEL CORP

Inventor： SHAEFFER GAD ,  RAIKIN SHLOMO ,  BASSIN VADIM

IPC: G06F9/06 ,  G06F9/46 ,  G06F12/00 ,  G06F12/06

公开(公告)号：BRPI0925055A2

公开(公告)日：2015-07-28

申请号：BRPI0925055

申请日：2009-06-26

Applicant: INTEL CORP

Inventor： SHEAFFER GAD ,  GRAY JAN ,  SMITH BURTON ,  ADL-TABATABAI ALI-REZA ,  GEVA ROBERT ,  BASSIN VADIM ,  CALLAHAN DAVID ,  NI YANG ,  SAHA BRATIN ,  TAILLEFER MARTIN ,  RAIKIN SHLOMO ,  YAMADA KOICHI ,  WANG LANDY ,  KISHAN ARUN

IPC: G06F9/06 ,  G06F9/44 ,  G06F9/46 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F13/00 ,  G06F15/00