公开(公告)号：JP2004152319A

公开(公告)日：2004-05-27

申请号：JP2003417826

申请日：2003-12-16

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： LIN DERRICK ,  VAKKALAGADDA ROMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI HIDEKAZU ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: PROBLEM TO BE SOLVED: To use a single physical register file under an alias to execute a floating point instruction and a pack data instruction. SOLUTION: A first instruction is received, it is determined whether the first instruction is the floating point instruction or a second type instruction, and it is determined whether a processor including first and second pairs of physical registers is in a floating point mode or in a second type mode. If the processor is in the second type mode when the first instruction is the floating point instruction, transition to the floating point mode is carried out, and the floating point instruction is operated by using the first pair of physical registers. If the processor is not in the floating point mode, transition to the second type mode is carried out, and the second type instruction is operated by using the second pair of physical registers partially under an alias to the first pair of physical registers so that the first pair of physical registers and the second pair of physical registers appear to be a single logical register file logically. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2012053898A

公开(公告)日：2012-03-15

申请号：JP2011234826

申请日：2011-10-26

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： MITTAL MILLIND

IPC: G06F12/14 ,  G06F21/00 ,  G06F21/22 ,  G06F21/24

CPC classification number: G06F21/72 ,  G06F12/1408 ,  G06F12/1441 ,  G06F12/1491 ,  G06F21/60 ,  G06F21/602

Abstract: PROBLEM TO BE SOLVED: To guarantee secure execution of a computer against various types of threats.SOLUTION: An apparatus for secure execution using a secure memory partition comprises: a non-volatile memory to store a verification execution instruction 242; a system memory 220 having a secure partition 223; and a processor 210 coupled to the non-volatile memory and the system memory 220. The processor 210 comprises: an on-chip basic input/output system (BIOS) 215 including a bootstrap security logic 241; and an execution unit 211 coupled to the on-chip BIOS 215 and the system memory 220 and configured to perform operation specified by the bootstrap security logic 241. The operation includes a step of copying the verification execution instruction 242 from the non-volatile memory to the secure partition and a step of verifying the authenticity of the verification execution instruction 242.

Abstract translation: 要解决的问题：保证计算机对各种威胁的安全执行。 解决方案：一种使用安全存储器分区进行安全执行的装置，包括：用于存储验证执行指令242的非易失性存储器; 具有安全分隔件223的系统存储器220; 以及耦合到非易失性存储器和系统存储器220的处理器210.处理器210包括：片上基本输入/输出系统（BIOS）215，其包括自举安全逻辑241; 以及耦合到片上BIOS 215和系统存储器220并被配置为执行由引导安全逻辑241指定的操作的执行单元211.该操作包括将验证执行指令242从非易失性存储器复制到 安全分区和验证验证执行指令242的真实性的步骤。版权所有：（C）2012，JPO＆INPIT

公开(公告)号：JP2004152318A

公开(公告)日：2004-05-27

申请号：JP2003417823

申请日：2003-12-16

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： LIN DERRICK ,  VAKKALAGADDA ROMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI HIDEKAZU ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: PROBLEM TO BE SOLVED: To install a set of instructions in a processor for processing pack data for furnishing compatibility with existing software and hardware. SOLUTION: For executing both of a set of pack data instructions and a set of floating point instructions on contents, which are aliased partially at least and correspond to a plurality of tags, of a single logical register file, the set of pack data instructions are executed before execution of the set of floating point instructions. At a certain time between a start of execution of a first instruction in the set of pack data instructions and execution of a first instruction in the set of floating point instructions, a plurality of tags matching an alias register in at least a single logical register file are changed into a non-empty condition, and the tags determine whether the register in a signal logical register file is empty or not. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2006172486A

公开(公告)日：2006-06-29

申请号：JP2005364534

申请日：2005-12-19

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： PELEG ALEXANDER ,  YAAKOV YAARI ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY

IPC: G06F5/00 ,  G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  G06F9/30 ,  G06F9/305 ,  G06F9/315 ,  G06F9/38

CPC classification number: G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30167

Abstract: PROBLEM TO BE SOLVED: To perform a shift operation on a packed data type. SOLUTION: An apparatus for arithmetic operation is provided with: a shifter which performs a shift operation on a first packed data having a plurality of first data elements by a shift count in order to produce a second packed data having a plurality of second data elements; and a correction circuit which replaces at least one number of each of the plurality of second data elements and replaces all the replaced numbers corresponding to the shifted data element with number having the same value even in any data element of the shifted data elements. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：对打包数据类型执行移位操作。 解决方案：一种用于算术运算的装置具有：移位器，其通过移位计数对具有多个第一数据元素的第一打包数据执行移位操作，以便产生具有多个第二数据元素的第二打包数据 数据元素; 以及校正电路，其替换多个第二数据元素中的每一个的至少一个，并且即使在移位的数据元素的任何数据元素中，也替换与具有相同值的数字的移位数据元素相对应的所有替换数字。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004145898A

公开(公告)日：2004-05-20

申请号：JP2003417830

申请日：2003-12-16

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： BISTRY DAVID ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  DULONG CAROLE ,  KOWASHI HIDEKAZU ,  MITTAL MILLIND ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: PROBLEM TO BE SOLVED: To propose a method and a device for a transition instruction to a register file. SOLUTION: A transition instruction marking the end of a block including a pack data instruction operated to data stored in a logic register is received. A register in a logic register file shows whether a plurality of tags related to the logic register file are empty or not by responding to execution of a scalar floating point instruction for changing the data included in the logic register file. The plurality of tags come to show empty in response to the transition instruction. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2006185453A

公开(公告)日：2006-07-13

申请号：JP2006009928

申请日：2006-01-18

Applicant: INTEL CORP

Inventor： LIN DERRICK ,  VAKKALAGADDA ROMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI HIDEKAZU ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/305 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

Abstract: PROBLEM TO BE SOLVED: To incorporate a set of instructions for processing packed data in a processor so as to have compatibility with existing software and hardware. SOLUTION: Both of a set of packed data instructions are performed before performance of floating point instruction to contents of a single logic register file which is at least partially aliased and to which a plurality of tags correspond, at a point of time between staring of performance of a first instruction of the packed data instruction set and completion of performance of a first instruction of a floating point instruction set, the plurality of tags corresponding to the aliased register in at least a single logic register file are changed to a not empty state and the tag identifies whether or not the register in the single logic register file is empty. COPYRIGHT: (C)2006,JPO&NCIPI

公开(公告)号：JP2006107463A

公开(公告)日：2006-04-20

申请号：JP2005248479

申请日：2005-08-29

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： PELEG ALEXANDER D ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY ,  DULONG CAROLE ,  KOWASHI HIDEKAZU ,  WITT WOLF ,  LIN DERRICK CHU ,  BINDAL AHMET ,  FISHER STEPHEN A ,  BUI TUAN H

IPC: G06F7/53 ,  G06F9/305 ,  G06F5/00 ,  G06F7/00 ,  G06F7/48 ,  G06F7/483 ,  G06F7/49 ,  G06F7/52 ,  G06F7/533 ,  G06F7/544 ,  G06F7/57 ,  G06F9/302 ,  G06F9/38 ,  G06F15/78 ,  G06F17/14 ,  G06F17/16 ,  G06T1/20

CPC classification number: G06F7/5324 ,  G06F7/4812 ,  G06F7/49921 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F15/7857 ,  G06F17/147 ,  G06F17/16 ,  G06F2207/3828 ,  G06T1/20

Abstract: PROBLEM TO BE SOLVED: To execute a function for multiplying two complex numbers by one multiply accumulate instruction. SOLUTION: A multiply-add circuit includes first (810), second (811), third (812), and fourth multipliers (813), wherein each of the multipliers receives a corresponding set of the above data elements. The multiply-add circuit further includes a first adder (850) coupled to the first and second multipliers (810 and 811), and second adder (851) coupled to the third and fourth multipliers (812 and 813). A third storage area (871) is coupled to the adders (850 and 851). The third storage area (871) includes a first and second field for saving output of the first and second adders (850 and 851), respectively, as first and second data elements of a third packed data. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：执行将两个复数乘以一个乘法累加指令的函数。 解决方案：乘法加法电路包括第一（810），第二（811），第三（812）和第四乘法器（813），其中每个乘法器接收上述数据元素的对应集合。 乘法电路还包括耦合到第一和第二乘法器（810和811）的第一加法器（850）和耦合到第三和第四乘法器（812和813）的第二加法器（851）。 第三存储区域（871）耦合到加法器（850和851）。 第三存储区域（871）包括用于分别保存第一和第二加法器（850和851）的输出的第一和第二字段作为第三打包数据的第一和第二数据元素。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：WO0175564A3

公开(公告)日：2003-01-16

申请号：PCT/US0108891

申请日：2001-03-21

Applicant: INTEL CORP ,  HERBERT HOWARD C ,  GRAWROCK DAVID W ,  ELLISON CARL M ,  GOLLIVER ROGER A ,  LIN DERRICK C ,  MCKEEN FRANCIS X ,  NEIGER GILBERT ,  RENERIS KEN ,  SUTTON JAMES A ,  THAKKAR SHREEKANT S ,  MITTAL MILLIND

Inventor： HERBERT HOWARD C ,  GRAWROCK DAVID W ,  ELLISON CARL M ,  GOLLIVER ROGER A ,  LIN DERRICK C ,  MCKEEN FRANCIS X ,  NEIGER GILBERT ,  RENERIS KEN ,  SUTTON JAMES A ,  THAKKAR SHREEKANT S ,  MITTAL MILLIND

IPC: G06F1/00 ,  G06F12/14 ,  G06F21/00

CPC classification number: G06F21/305 ,  G06F9/30189 ,  G06F12/1491 ,  G06F21/35 ,  G06F21/53 ,  G06F21/57 ,  G06F21/575 ,  G06F21/64 ,  G06F21/74 ,  G06F2221/2101 ,  G06F2221/2103 ,  G06F2221/2105 ,  G06F2221/2149

Abstract: In one embodiment, a method of remote attestation for a special mode of operation. The method comprises storing an audit log within protected memory of a platform. The audit log is a listing of data representing each of a plurality of IsoX software modules loaded into the platform. The audit log is retrieved from the protected memory in response to receiving a remote attestation request from a remotely located platform. Then, the retrieved audit log is digitally signed to produce a digital signature for transfer to the remotely located platform.

Abstract translation: 在一个实施例中，用于特殊操作模式的远程证明的方法。 该方法包括将审核日志存储在平台的受保护的存储器内。 审计日志是表示加载到平台中的多个IsoX软件模块中的每一个的数据的列表。 响应于从远程位置的平台接收远程认证请求，从受保护的内存中检索审核日志。 然后，检索的审核日志进行数字签名，以产生数字签名，以转移到位于远程的平台。

公开(公告)号：WO0175565A3

公开(公告)日：2002-06-27

申请号：PCT/US0109371

申请日：2001-03-23

Applicant: INTEL CORP ,  ELLISON CARL M ,  GOLLIVER ROGER A ,  HERBERT HOWARD C ,  LIN DERRICK C ,  MCKEEN FRANCIS X ,  NEIGER GILBERT ,  RENERIS KEN ,  SUTTON JAMES A ,  THAKKAR SHREEKANT S ,  MITTAL MILLIND

Inventor： ELLISON CARL M ,  GOLLIVER ROGER A ,  HERBERT HOWARD C ,  LIN DERRICK C ,  MCKEEN FRANCIS X ,  NEIGER GILBERT ,  RENERIS KEN ,  SUTTON JAMES A ,  THAKKAR SHREEKANT S ,  MITTAL MILLIND

IPC: G06F9/46 ,  G06F1/00 ,  G06F9/48 ,  G06F21/00

CPC classification number: G06F21/53 ,  G06F2221/2105

Abstract: A technique is provided to execute isolated instructions according to an embodiment of the present invention. An execution unit executes an isolated instruction in a processor operating in a platform. The processor is configured in one of a normal execution mode and an isolated execution mode. A parameter storage containing at least one parameter to support execution of the isolated instruction when the processor is configured in the isolated execution mode.

Abstract translation: 提供了根据本发明的实施例的执行隔离指令的技术。 执行单元在平台中操作的处理器中执行隔离指令。 处理器配置为正常执行模式和隔离执行模式之一。 当处理器被配置为隔离执行模式时，包含至少一个参数以支持执行隔离指令的参数存储器。

公开(公告)号：WO0203208A3

公开(公告)日：2003-03-20

申请号：PCT/US0118447

申请日：2001-06-07

Applicant: INTEL CORP

Inventor： MITTAL MILLIND

IPC: G06F12/14 ,  G06F21/00 ,  G06F21/22 ,  G06F21/24 ,  G06F1/00

CPC classification number: G06F21/72 ,  G06F12/1408 ,  G06F12/1441 ,  G06F12/1491 ,  G06F21/60 ,  G06F21/602

Abstract: A processor capable of secure execution. The processor contains an execution unit and secure partition logic that secures a partition in memory. The processor also contains cryptographic logic coupled to the execution unit that encrypts and decrypts secure data and code.

Abstract translation: 能够安全执行的处理器。 该处理器包含一个执行单元和安全的分区逻辑，将分区保存在内存中。 处理器还包含耦合到执行单元的加密逻辑，其加密和解密安全数据和代码。