公开(公告)号：JP2004152319A

公开(公告)日：2004-05-27

申请号：JP2003417826

申请日：2003-12-16

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： LIN DERRICK ,  VAKKALAGADDA ROMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI HIDEKAZU ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: PROBLEM TO BE SOLVED: To use a single physical register file under an alias to execute a floating point instruction and a pack data instruction. SOLUTION: A first instruction is received, it is determined whether the first instruction is the floating point instruction or a second type instruction, and it is determined whether a processor including first and second pairs of physical registers is in a floating point mode or in a second type mode. If the processor is in the second type mode when the first instruction is the floating point instruction, transition to the floating point mode is carried out, and the floating point instruction is operated by using the first pair of physical registers. If the processor is not in the floating point mode, transition to the second type mode is carried out, and the second type instruction is operated by using the second pair of physical registers partially under an alias to the first pair of physical registers so that the first pair of physical registers and the second pair of physical registers appear to be a single logical register file logically. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2004152318A

公开(公告)日：2004-05-27

申请号：JP2003417823

申请日：2003-12-16

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： LIN DERRICK ,  VAKKALAGADDA ROMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI HIDEKAZU ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: PROBLEM TO BE SOLVED: To install a set of instructions in a processor for processing pack data for furnishing compatibility with existing software and hardware. SOLUTION: For executing both of a set of pack data instructions and a set of floating point instructions on contents, which are aliased partially at least and correspond to a plurality of tags, of a single logical register file, the set of pack data instructions are executed before execution of the set of floating point instructions. At a certain time between a start of execution of a first instruction in the set of pack data instructions and execution of a first instruction in the set of floating point instructions, a plurality of tags matching an alias register in at least a single logical register file are changed into a non-empty condition, and the tags determine whether the register in a signal logical register file is empty or not. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2006172486A

公开(公告)日：2006-06-29

申请号：JP2005364534

申请日：2005-12-19

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： PELEG ALEXANDER ,  YAAKOV YAARI ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY

IPC: G06F5/00 ,  G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  G06F9/30 ,  G06F9/305 ,  G06F9/315 ,  G06F9/38

CPC classification number: G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30167

Abstract: PROBLEM TO BE SOLVED: To perform a shift operation on a packed data type. SOLUTION: An apparatus for arithmetic operation is provided with: a shifter which performs a shift operation on a first packed data having a plurality of first data elements by a shift count in order to produce a second packed data having a plurality of second data elements; and a correction circuit which replaces at least one number of each of the plurality of second data elements and replaces all the replaced numbers corresponding to the shifted data element with number having the same value even in any data element of the shifted data elements. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：对打包数据类型执行移位操作。 解决方案：一种用于算术运算的装置具有：移位器，其通过移位计数对具有多个第一数据元素的第一打包数据执行移位操作，以便产生具有多个第二数据元素的第二打包数据 数据元素; 以及校正电路，其替换多个第二数据元素中的每一个的至少一个，并且即使在移位的数据元素的任何数据元素中，也替换与具有相同值的数字的移位数据元素相对应的所有替换数字。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2004145898A

公开(公告)日：2004-05-20

申请号：JP2003417830

申请日：2003-12-16

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： BISTRY DAVID ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  DULONG CAROLE ,  KOWASHI HIDEKAZU ,  MITTAL MILLIND ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: PROBLEM TO BE SOLVED: To propose a method and a device for a transition instruction to a register file. SOLUTION: A transition instruction marking the end of a block including a pack data instruction operated to data stored in a logic register is received. A register in a logic register file shows whether a plurality of tags related to the logic register file are empty or not by responding to execution of a scalar floating point instruction for changing the data included in the logic register file. The plurality of tags come to show empty in response to the transition instruction. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2006185453A

公开(公告)日：2006-07-13

申请号：JP2006009928

申请日：2006-01-18

Applicant: INTEL CORP

Inventor： LIN DERRICK ,  VAKKALAGADDA ROMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI HIDEKAZU ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/305 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

Abstract: PROBLEM TO BE SOLVED: To incorporate a set of instructions for processing packed data in a processor so as to have compatibility with existing software and hardware. SOLUTION: Both of a set of packed data instructions are performed before performance of floating point instruction to contents of a single logic register file which is at least partially aliased and to which a plurality of tags correspond, at a point of time between staring of performance of a first instruction of the packed data instruction set and completion of performance of a first instruction of a floating point instruction set, the plurality of tags corresponding to the aliased register in at least a single logic register file are changed to a not empty state and the tag identifies whether or not the register in the single logic register file is empty. COPYRIGHT: (C)2006,JPO&NCIPI

公开(公告)号：JP2006107463A

公开(公告)日：2006-04-20

申请号：JP2005248479

申请日：2005-08-29

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： PELEG ALEXANDER D ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY ,  DULONG CAROLE ,  KOWASHI HIDEKAZU ,  WITT WOLF ,  LIN DERRICK CHU ,  BINDAL AHMET ,  FISHER STEPHEN A ,  BUI TUAN H

IPC: G06F7/53 ,  G06F9/305 ,  G06F5/00 ,  G06F7/00 ,  G06F7/48 ,  G06F7/483 ,  G06F7/49 ,  G06F7/52 ,  G06F7/533 ,  G06F7/544 ,  G06F7/57 ,  G06F9/302 ,  G06F9/38 ,  G06F15/78 ,  G06F17/14 ,  G06F17/16 ,  G06T1/20

CPC classification number: G06F7/5324 ,  G06F7/4812 ,  G06F7/49921 ,  G06F7/5338 ,  G06F7/5443 ,  G06F9/30014 ,  G06F9/30036 ,  G06F15/7857 ,  G06F17/147 ,  G06F17/16 ,  G06F2207/3828 ,  G06T1/20

Abstract: PROBLEM TO BE SOLVED: To execute a function for multiplying two complex numbers by one multiply accumulate instruction. SOLUTION: A multiply-add circuit includes first (810), second (811), third (812), and fourth multipliers (813), wherein each of the multipliers receives a corresponding set of the above data elements. The multiply-add circuit further includes a first adder (850) coupled to the first and second multipliers (810 and 811), and second adder (851) coupled to the third and fourth multipliers (812 and 813). A third storage area (871) is coupled to the adders (850 and 851). The third storage area (871) includes a first and second field for saving output of the first and second adders (850 and 851), respectively, as first and second data elements of a third packed data. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：执行将两个复数乘以一个乘法累加指令的函数。 解决方案：乘法加法电路包括第一（810），第二（811），第三（812）和第四乘法器（813），其中每个乘法器接收上述数据元素的对应集合。 乘法电路还包括耦合到第一和第二乘法器（810和811）的第一加法器（850）和耦合到第三和第四乘法器（812和813）的第二加法器（851）。 第三存储区域（871）耦合到加法器（850和851）。 第三存储区域（871）包括用于分别保存第一和第二加法器（850和851）的输出的第一和第二字段作为第三打包数据的第一和第二数据元素。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：EP0847551A4

公开(公告)日：2001-11-21

申请号：EP96926742

申请日：1996-07-17

Applicant: INTEL CORP

Inventor： PELEG ALEXANDER D ,  YAARI YAACOV ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY ,  GLEW ANDREW F ,  DULONG CAROLE ,  KOWASHI EIICHI ,  WITT WOLF

IPC: G06F5/00 ,  G06F7/544 ,  G06F7/57 ,  G06F7/60 ,  G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F9/38 ,  G06F15/78 ,  G06F7/00 ,  G06F7/02 ,  G06F7/38 ,  G06F7/50 ,  G06F7/52

CPC classification number: G06F7/57 ,  G06F7/49921 ,  G06F7/49994 ,  G06F7/5443 ,  G06F7/607 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F17/10 ,  G06F17/147 ,  G06F2207/382 ,  G06F2207/3828

Abstract: An apparatus for including in a processor a set of instructions that support operations on packed data required by typical multimedia applications. In one embodiment, the invention includes a processor having a storage area (150), a decoder (165), and a plurality of circuits (130). The plurality of circuits provide for the execution of a number of instructions to manipulate packed data. In this embodiment, these instructions include pack, unpack, packed multiply, packed add, packed subtract, packed compare, and packed shift.

公开(公告)号：EP0795155A4

公开(公告)日：1999-08-11

申请号：EP95944602

申请日：1995-12-01

Applicant: INTEL CORP

Inventor： PELEG ALEXANDER ,  YAARI YAAKOV ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY

IPC: G06F9/305 ,  G06F5/00 ,  G06F7/52 ,  G06F9/30 ,  G06F9/302 ,  G06F9/38

CPC classification number: G06F7/53 ,  G06F7/49921 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3885 ,  G06F2207/3828

公开(公告)号：EP0870224A4

公开(公告)日：1999-02-10

申请号：EP96945274

申请日：1996-12-24

Applicant: INTEL CORP

Inventor： DULONG CAROLE ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BUI TUAN H ,  KOWASHI EIICHI ,  MITTAL MILLIND ,  EITAN BENNY ,  FISHER STEPHEN A ,  MAYTAL BENNY

IPC: G06F7/544 ,  G06F9/302 ,  G06F7/38 ,  G06F7/52 ,  G06F15/00 ,  G06F15/76 ,  G06F15/78 ,  G06F15/80

CPC classification number: G06F9/30036 ,  G06F7/5443 ,  G06F9/30014 ,  G06F2207/3828

Abstract: A computer system which includes a multimedia input device which generates an audio or video input signal and a processor coupled to the multimedia input device. The system further includes a storage device coupled to the processor and having stored therein a signal processing routine for multiplying and accumulating input values representative of the audio or video input signal. The signal processing routine, when executed by the processor, causes the processor to perform several steps. These steps include performing a packed multiply add on a first set of values packed into a first source and a second set of values packed into a second source each representing input signals to generate a packed intermediate result. The packed intermediate result is added to an accumulator to generate a packed accumulated result in the accumulator. These steps may be iterated with the first set of values and portions of the second set of values to the accumulator to generate the packed accumulated result. Subsequent thereto, the packed accumulated result in the accumulator is unpacked into a first result and a second result and the first result and the second result are added together to generate an accumulated result.

公开(公告)号：EP0795153A4

公开(公告)日：2001-11-14

申请号：EP95943362

申请日：1995-12-01

Applicant: INTEL CORP

Inventor： PELEG ALEXANDER ,  YAARI YAAKOV ,  MITTAL MILLIND ,  MENNEMEIER LARRY M ,  EITAN BENNY

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F9/318 ,  G06F7/14

CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

Abstract: A processor includes a first register (209) for storing a first packed data, a decoder (202), and a functional unit (203). The decoder has a control signal input (207) for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation, and the second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder (202) and the register (209). The functional unit performs the pack operation and the unpack operation using the first packed data as well as move operation.