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1.发明专利
公开(公告)号：JP2006185453A
公开(公告)日：2006-07-13
申请号：JP2006009928
申请日：2006-01-18
Applicant: INTEL CORP
Inventor： LIN DERRICK , VAKKALAGADDA ROMAMOHAN R , GLEW ANDREW F , MENNEMEIER LARRY M , PELEG ALEXANDER D , BISTRY DAVID , MITTAL MILLIND , DULONG CAROLE , KOWASHI HIDEKAZU , EITAN BENNY
Abstract: PROBLEM TO BE SOLVED: To incorporate a set of instructions for processing packed data in a processor so as to have compatibility with existing software and hardware. SOLUTION: Both of a set of packed data instructions are performed before performance of floating point instruction to contents of a single logic register file which is at least partially aliased and to which a plurality of tags correspond, at a point of time between staring of performance of a first instruction of the packed data instruction set and completion of performance of a first instruction of a floating point instruction set, the plurality of tags corresponding to the aliased register in at least a single logic register file are changed to a not empty state and the tag identifies whether or not the register in the single logic register file is empty. COPYRIGHT: (C)2006,JPO&NCIPI
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公开(公告)号：JP2004152319A
公开(公告)日：2004-05-27
申请号：JP2003417826
申请日：2003-12-16
Applicant: Intel Corp , インテル・コーポレーション
Inventor： LIN DERRICK , VAKKALAGADDA ROMAMOHAN R , GLEW ANDREW F , MENNEMEIER LARRY M , PELEG ALEXANDER D , BISTRY DAVID , MITTAL MILLIND , DULONG CAROLE , KOWASHI HIDEKAZU , EITAN BENNY
CPC classification number: G06F9/30123 , G06F9/30036 , G06F9/30109 , G06F9/30134 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
Abstract: PROBLEM TO BE SOLVED: To use a single physical register file under an alias to execute a floating point instruction and a pack data instruction. SOLUTION: A first instruction is received, it is determined whether the first instruction is the floating point instruction or a second type instruction, and it is determined whether a processor including first and second pairs of physical registers is in a floating point mode or in a second type mode. If the processor is in the second type mode when the first instruction is the floating point instruction, transition to the floating point mode is carried out, and the floating point instruction is operated by using the first pair of physical registers. If the processor is not in the floating point mode, transition to the second type mode is carried out, and the second type instruction is operated by using the second pair of physical registers partially under an alias to the first pair of physical registers so that the first pair of physical registers and the second pair of physical registers appear to be a single logical register file logically. COPYRIGHT: (C)2004,JPO
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公开(公告)号：JP2004152318A
公开(公告)日：2004-05-27
申请号：JP2003417823
申请日：2003-12-16
Applicant: Intel Corp , インテル・コーポレーション
Inventor： LIN DERRICK , VAKKALAGADDA ROMAMOHAN R , GLEW ANDREW F , MENNEMEIER LARRY M , PELEG ALEXANDER D , BISTRY DAVID , MITTAL MILLIND , DULONG CAROLE , KOWASHI HIDEKAZU , EITAN BENNY
CPC classification number: G06F9/30123 , G06F9/30036 , G06F9/30109 , G06F9/30134 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
Abstract: PROBLEM TO BE SOLVED: To install a set of instructions in a processor for processing pack data for furnishing compatibility with existing software and hardware. SOLUTION: For executing both of a set of pack data instructions and a set of floating point instructions on contents, which are aliased partially at least and correspond to a plurality of tags, of a single logical register file, the set of pack data instructions are executed before execution of the set of floating point instructions. At a certain time between a start of execution of a first instruction in the set of pack data instructions and execution of a first instruction in the set of floating point instructions, a plurality of tags matching an alias register in at least a single logical register file are changed into a non-empty condition, and the tags determine whether the register in a signal logical register file is empty or not. COPYRIGHT: (C)2004,JPO
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公开(公告)号：ZA9610677B
公开(公告)日：1997-06-24
申请号：ZA9610677
申请日：1996-12-19
Applicant: INTEL CORP
Inventor： GLEW ANDREW F , MENNEMEIER LARRY M , PELEG ALEXANDER D , BISTRY DAVID , MITTAL MILLIND , DULONG CAROLE , KOWASHI EIICHI , EITAN BENNY , LIN DERRICK , VAKKALAGADDA ROMAMOHAN R
Abstract: A method for executing different sets of instructions that cause a processor to perform different data type operations in a manner that is invisible to various operating system techniques, that promotes good programming practices, and that is invisible to existing software conventions. According to one aspect of the invention, a data processing apparatus executes a first set of instructions of a first instruction type on what at least logically appears to software as a single logical register file. While the data processing apparatus is executing the first set of instructions, the single logical register file appears to be operated as a flat register file. In addition, the data processing apparatus executes a first instruction of a second instruction type using the logical register file. However, while the data processing apparatus is executing the first instruction, the logical register file appears to be operated as a stack referenced register file. Furthermore, the data processing apparatus alters all tags in a set of tags corresponding to the single logical register file to a non-empty state sometime between starting the execution of the first set of instructions and completing the execution of the first instruction. The tags identifying whether registers in the single logical register file are empty or non-empty.
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