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公开(公告)号：WO2011081846A2
公开(公告)日：2011-07-07
申请号：PCT/US2010059853
申请日：2010-12-10
Applicant: INTEL CORP , DUNNING DAVE , CASPER BRYAN , MOONEY RANDY , MANSURI MOZHGAN , JAUSSI JAMES E
Inventor： DUNNING DAVE , CASPER BRYAN , MOONEY RANDY , MANSURI MOZHGAN , JAUSSI JAMES E
IPC: G11C5/02
CPC classification number: G06F11/1076 , G11C5/02 , G11C29/12 , H01L2224/16145 , H03M13/15 , H03M13/152
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.
Abstract translation: 本发明的实施例一般涉及用于混合存储器的系统，方法和装置。 在一个实施例中，混合存储器可以包括封装衬底。 混合存储器还可以包括附接到封装衬底的第一侧的混合存储器缓冲芯片。 高速输入/输出（HSIO）逻辑支持与处理器的HSIO接口。 混合存储器还包括在HSIO接口上支持分组处理协议的分组处理逻辑。 此外，混合存储器还具有垂直堆叠在混合存储器缓冲器上的一个或多个存储器片。
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公开(公告)号：DE112006001042T5
公开(公告)日：2008-04-03
申请号：DE112006001042
申请日：2006-04-25
Applicant: INTEL CORP
Inventor： MARTIN AARON , HANUOLU PARVAN , MOONEY RANDY
Abstract: A continuous-time equalizer includes a first transconductance circuit to set a gain of an amplified signal in a link and a second transconductance circuit to set a zero frequency in a transfer function of the equalizer. The zero frequency controls a frequency range of the signal amplified in the link based on the gain set by the first transconductance circuit.
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公开(公告)号：GB2441241A
公开(公告)日：2008-02-27
申请号：GB0719677
申请日：2006-04-25
Applicant: INTEL CORP
Inventor： MARTIN AARON , HANUOLU PARVAN , MOONEY RANDY
Abstract: A continuous-time equalizer includes a first transconductance circuit to set a gain of an amplified signal in a link and a second transconductance circuit to set a zero frequency in a transfer function of the equalizer. The zero frequency controls a frequency range of the signal amplified in the link based on the gain set by the first transconductance circuit.
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公开(公告)号：EP2519948A4
公开(公告)日：2014-01-08
申请号：EP10841482
申请日：2010-12-10
Applicant: INTEL CORP
Inventor： DUNNING DAVE , CASPER BRYAN , MOONEY RANDY , MANSURI MOZHGAN , JAUSSI JAMES E
IPC: G11C5/02
CPC classification number: G06F11/1076 , G11C5/02 , G11C29/12 , H01L2224/16145 , H03M13/15 , H03M13/152
Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for hybrid memory. In one embodiment, a hybrid memory may include a package substrate. The hybrid memory may also include a hybrid memory buffer chip attached to the first side of the package substrate. High speed input/output (HSIO) logic supporting a HSIO interface with a processor. The hybrid memory also includes packet processing logic to support a packet processing protocol on the HSIO interface. Additionally, the hybrid memory also has one or more memory tiles that are vertically stacked on the hybrid memory buffer.
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