公开(公告)号：KR20180021105A

公开(公告)日：2018-02-28

申请号：KR20187002080

申请日：2015-06-26

Applicant: INTEL CORP

Inventor： LIN KEVIN ,  BRISTOL ROBERT LINDSEY ,  MYERS ALAN M

IPC: H01L21/033 ,  H01L21/3213 ,  H01L21/768

CPC classification number: H01L21/32139 ,  H01L21/0334 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897

Abstract: 본발명의실시예들은텍스타일패터닝된하드마스크를형성하는방법들을포함한다. 실시예에서, 제1 하드마스크및 제2 하드마스크는상호접속층의최상부면위에교대하는패턴으로형성된다. 다음으로, 제1 하드마스크재료및 제2 하드마스크재료위에희생교차격자가형성될수 있다. 실시예에서, 제1 개구들을형성하기위해, 희생교차격자에의해커버되지않은제1 하드마스크재료의부분들이제거되고, 제3 하드마스크는제1 개구들내에배치된다. 다음으로, 실시예들은제2 개구들을형성하기위해, 희생교차격자에의해커버되지않은제2 하드마스크의부분들을통해에칭하는것을포함할수 있다. 제2 개구들은제4 하드마스크로채워질수 있다. 실시예에따르면, 제1, 제2, 제3, 및제4 하드마스크는서로에대해에칭선택성을갖는다. 실시예에서, 다음으로, 희생교차격자가제거될수 있다.

Abstract translation: 本发明的实施例包括形成纹理化图案化硬掩模的方法。 在一个实施例中，第一硬掩模和第二硬掩模在互连层的顶表面上以交替图案形成。 接下来，可以在第一硬掩模材料和第二硬掩模材料上形成牺牲交点晶格。 在一个实施例中，为了形成第一开口，去除未被牺牲交叉栅格覆盖的第一硬掩模材料的部分，并且第三硬掩模设置在第一开口内。 接下来，实施例可以包括蚀刻第二硬掩模的没有被牺牲交叉点光栅覆盖的部分以形成第二开口。 第二开口可以填充第四硬掩模。 根据一个实施例，第一，第二，第三和第四硬掩模彼此具有蚀刻选择性。 在一个实施例中，然后可以去除牺牲交叉点光栅。

公开(公告)号：AU5790800A

公开(公告)日：2001-01-31

申请号：AU5790800

申请日：2000-06-05

Applicant: INTEL CORP

Inventor： HUSSEIN MAKAREM A ,  MYERS ALAN M ,  RECCHIA CHARLES H ,  SIVAKUMAR SAM ,  KANDAS ANGELO W

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: A method of forming an interconnection including the steps of forming a sacrificial material (160) that comprises a physical property that is generally insensitive to a photoreaction in a via (150) through a dielectric material (130) to a masking material (120) over a conductive material (110). The method also includes forming a trench (180) over in the dielectric material over the via (150) and removing the sacrificial material (160) from the via.

公开(公告)号：GB2308234B

公开(公告)日：1999-04-14

申请号：GB9706661

申请日：1995-07-14

Applicant: INTEL CORP

Inventor： MYERS ALAN M ,  CHARVAT PETER K ,  LETSON THOMAS ,  YANG SHI-NING ,  BAI PENG

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.

公开(公告)号：GB2308234A

公开(公告)日：1997-06-18

申请号：GB9706661

申请日：1995-07-14

Applicant: INTEL CORP

Inventor： MYERS ALAN M ,  CHARVAT PETER K ,  LETSON THOMAS ,  YANG SHI-NING ,  BAI PENG

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.

公开(公告)号：AU3152195A

公开(公告)日：1996-05-06

申请号：AU3152195

申请日：1995-07-14

Applicant: INTEL CORP

Inventor： MYERS ALAN M ,  CHARVAT PETER K ,  LETSON THOMAS A ,  YANG SHI-NING ,  BAI PENG

IPC: H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/302

Abstract: A novel high performance and reliable interconnection structure for preventing via delamination. The interconnection structure of the present invention comprises a via connection which extends into and undercuts an underlying interconnection line to lock the via connection into the interconnection line.

公开(公告)号：MY138557A

公开(公告)日：2009-06-30

申请号：MYPI20044164

申请日：2004-10-11

Applicant: INTEL CORP

Inventor： KIM SARAH E ,  LIST R SCOTT ,  MAVEETY JAMES G ,  MYERS ALAN M ,  VU QUAT T

IPC: F04B17/00 ,  F04B19/00 ,  H01L23/473 ,  H01L25/065

Abstract: A STACK OF HEAT GENERATING INTEGRATED CIRCUIT CHIPS MAY BE PROVIDED WITH INTERVENING COOLING INTEGRATED CIRCUIT CHIPS. THE COOLING INTEGRATED CIRCUIT CHIPS MAY INCLUDE MICROCHANNELS FOR THE FLOW OF THE COOLING FLUID. THE COOLING FLUID MAY BE PUMPED USING THE INTEGRATED ELECTROSMOTIC PUMPS. REMOVAL OF COOLING FLUID GASES MAY BE ACCOMPLISHED USING INTEGRATED RE-COMBINERS IN SOME EMBODIMENTS.

公开(公告)号：MY138510A

公开(公告)日：2009-06-30

申请号：MYPI20044480

申请日：2004-10-29

Applicant: INTEL CORP

Inventor： KIM SARAH E ,  LIST R SCOTT ,  MAVEETY JAMES G ,  MYERS ALAN M ,  VU QUAT T ,  PRASHER RAVI ,  MAHAJAN RAVI ,  VANDENTOP GILROY

IPC: H01L23/473

Abstract: AN INTEGRATED CIRCUIT TO BE COOLED MAY BE ABUTTED IN FACE-TO-FACE ABUTMENT WITH A COOLING INTEGRATED CIRCUIT. THE COOLING INTEGRATED CIRCUIT MAY INCLUDE ELECTROOSMOTIC PUMPS (28) TO PUMP COOLING FLUID THROUGH THE COOLING INTEGRATED CIRCUITS VIA MICROCHANNELS (68A,68B) TO THEREBY COOL THE HEAT GENERATING INTEGRATED CIRCUIT. THE ELECTROOSMOTIC PUMPS (28) MAY BE FLUIDIC ALLY COUPLED TO EXTERNAL RADIATORS (132) WHICH EXTEND UPWARDLY AWAY FROM A PACKAGE (129) INCLUDING THE INTEGRATED CIRCUITS. IN PARTICULAR, THE EXTERNAL RADIATORS (132) MAY BE MOUNTED ON TUBES WHICH EXTEND THE RADIATORS AWAY FROM THE PACKAGE (129).FIG. 1

公开(公告)号：EP3084821A4

公开(公告)日：2017-09-13

申请号：EP14872705

申请日：2014-11-05

Applicant: INTEL CORP

Inventor： MYERS ALAN M ,  SINGH KANWAL JIT ,  BRISTOL ROBERT L ,  CHAWLA JASMEET S

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76879 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP3097582A4

公开(公告)日：2017-11-01

申请号：EP14879315

申请日：2014-12-09

Applicant: INTEL CORP

Inventor： JEZEWSKI CHRISTOPHER J ,  CHAWLA JASMEET S ,  SINGH KANWAL JIT ,  MYERS ALAN M ,  TAN ELIOT N ,  SCHENKER RICHARD E

IPC: H01L21/768

CPC classification number: H01L21/7688 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76886 ,  H01L21/76897 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Processes for forming interconnection layers having tight pitch interconnect structures within a dielectric layer, wherein trenches and vias used to form interconnect structures have relatively low aspect ratios prior to metallization. The low aspect ratios may reduce or substantially eliminate the potential of voids forming within the metallization material when it is deposited. Embodiments herein may achieve such relatively low aspect ratios through processes that allow for the removal of structures, which are utilized to form the trenches and the vias, prior to metallization.

公开(公告)号：EP3084820A4

公开(公告)日：2017-10-25

申请号：EP14872074

申请日：2014-10-30

Applicant: INTEL CORP

Inventor： BRISTOL ROBERT L ,  BLACKWELL JAMES M ,  MYERS ALAN M ,  SINGH KANWAL J

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/0338 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00