公开(公告)号：BR102014006301A2

公开(公告)日：2015-11-03

申请号：BR102014006301

申请日：2014-03-17

Applicant: INTEL CORP

Inventor： DIXON MARTIN G ,  RASH WILLIAM C ,  SANTIAGO YAZMIN A

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/455

Abstract: processadores, métodos e sistemas emuladores de instruções. em um aspecto, a presente invenção trata de um processador que inclui lógica de decodificação para receber uma primeira instrução e determinar que a primeira instruçâo deva ser emulada, o processador também inclui lógica de processador de instrução pós-decodificação ciente de modo de emulação acoplada à lógica de decodificação. a lógica de processador de instruçôes pós-decodificação ciente de modo de emulaç&o deve processar um ou mais sinais de controle decodificados a partir de uma instruçâo. a instruçao é uma de um conjunto de uma ou mais instruçôes utilizadas para emular a primeira instrução. um ou mais sinais de controle devem ser processados diferentemente pela lógica de processador de instruçào pós-decodificaçâo ciente de modo de emulaçao quando em um modo de emulação do que quando não no modo de emulação. outros aparelhos são também descritos, bem como métodos e sistemas

公开(公告)号：GB2514882A

公开(公告)日：2014-12-10

申请号：GB201404410

申请日：2014-03-13

Applicant: INTEL CORP

Inventor： RASH WILLIAM C ,  TOLL BRET L ,  HAHN SCOTT D ,  HINTON GLENN

IPC: G06F9/30

Abstract: A processor of an aspect includes decode logic (105) to receive a first instruction and to determine that the first instruction is to be emulated. The processor also includes emulation mode aware post-decode instruction processor logic (107) coupled with the decode logic. The emulation mode aware post-decode instruction processor logic is to process one or more control signals decoded from an instruction. The instruction is one of a set of one or more instructions used to emulate the first instruction. The one or more control signals are to be processed differently by the emulation mode aware post-decode instruction processor logic when in an emulation mode than when not in the emulation mode. Exceptions may be handled differently or different resources (processor, memory, security logic, random number generator logic, encryption logic) may be accessed. Other apparatus are also disclosed as well as methods and systems. The processor might not use microcode.

公开(公告)号：DE102014003690A1

公开(公告)日：2014-09-18

申请号：DE102014003690

申请日：2014-03-14

Applicant: INTEL CORP

Inventor： RASH WILLIAM C ,  TOLL BRET L ,  HAHN SCOTT D ,  HINTON GLENN J

IPC: G06F9/30 ,  G06F9/318

Abstract: Ein Prozessor enthält unter einem Aspekt Dekodierlogik zum Erhalten eines ersten Befehls und zum Bestimmen, dass der erste Befehl emuliert werden soll. Der Prozessor enthält auch emulationsmodusbewusste Nachdekodier-Befehlsprozessorlogik, die mit der Dekodierlogik gekoppelt ist. Die emulationsmodusbewusste Nachdekodier-Befehlsprozessorlogik soll ein oder mehrere Steuersignale verarbeiten, die aus einem Befehl dekodiert werden. Der Befehl ist einer aus einem Satz von einem oder mehreren Befehlen, die zum Emulieren des ersten Befehls verwendet werden. Die ein oder mehreren Steuersignale sollen durch die emulationsmodusbewusste Nachdekodier-Befehlsprozessorlogik anders verarbeitet werden, wenn ein Emulationsmodus vorliegt, als wenn kein Emulationsmodus vorliegt. Andere Vorrichtungen sind ebenfalls offenbart, ebenso wie Verfahren und Systeme.

公开(公告)号：DE102014003671A1

公开(公告)日：2014-09-18

申请号：DE102014003671

申请日：2014-03-14

Applicant: INTEL CORP

Inventor： DIXON MARTIN G ,  RASH WILLIAM C ,  SANTIAGO YAZMIN A

IPC: G06F9/30

Abstract: Ein Prozessor eines Aspekts beinhaltet mehrere logische Prozessoren. Ein erster der mehreren logischen Prozessoren dient dazu, Software auszuführen, die einen Speicherzugriffsynchronisations-Befehl beinhaltet, der die Zugriffe auf einen Speicher synchronisieren soll. Der Prozessor beinhaltet außerdem eine Logik zur Entspannung der Speicherzugriffsynchronisation, die dazu dient, den Speicherzugriffsynchronisations-Befehl daran zu hindern, Zugriffe auf den Speicher zu synchronisieren, wenn sich der Prozessor in einem entspannten Speicherzugriffsynchronisationsmodus befindet.

公开(公告)号：GB2512470B

公开(公告)日：2015-06-03

申请号：GB201402776

申请日：2014-02-17

Applicant: INTEL CORP

Inventor： RASH WILLIAM C ,  HAHN SCOTT D ,  TOLL BRET L ,  HINTON GLENN J

IPC: G06F9/46 ,  G06F12/08

Abstract: Systems and methods for implementing transactional memory access. An example method may comprise initiating a memory access transaction; executing a transactional read operation, using a first buffer associated with a memory access tracking logic, with respect to a first memory location, and/or a transactional write operation, using a second buffer associated with the memory access tracking logic, with respect to a second memory location; executing a non-transactional read operation with respect to a third memory location, and/or a non-transactional write operation with respect to a fourth memory location; responsive to detecting, by the memory access tracking logic, access by a device other than the processor to the first memory location or the second memory location, aborting the memory access transaction; and completing, irrespectively of the state of the third memory location and the fourth memory location, the memory access transaction responsive to failing to detect a transaction aborting condition.

公开(公告)号：GB2512470A

公开(公告)日：2014-10-01

申请号：GB201402776

申请日：2014-02-17

Applicant: INTEL CORP

Inventor： RASH WILLIAM C ,  HAHN SCOTT D ,  TOLL BRET L ,  HINTON GLENN J

IPC: G06F9/46 ,  G06F12/08

Abstract: Disclosed are systems and methods of implementing transactional memory access. The method starts by a processor initiating a memory access transaction, executing a transactional read operation, using a first buffer associated with a memory access tracking logic, with respect to a first memory location, and/or a transactional write operation, using a second buffer associated with the memory access tracking logic, with respect to a second memory location. Next, a non-transactional read operation with respect to a third memory location, and/or a non-transactional write operation with respect to a fourth memory location, is executed. If access by a device other than the processor to the first or second memory location is detected by the memory access tracking logic, the memory access transaction is aborted. If the logic fails to detect a transaction aborting condition, irrespectively of the state of the third and fourth memory locations, the memory access transaction is completed.

公开(公告)号：EP3014422A4

公开(公告)日：2017-03-01

申请号：EP14816582

申请日：2014-06-19

Applicant: INTEL CORP

Inventor： RASH WILLIAM C ,  SANTIAGO YAZMIN A ,  DIXON MARTIN GUY

IPC: G06F9/312

CPC classification number: G06F9/30145 ,  G06F9/30043 ,  G06F9/30189 ,  G06F9/3836

Abstract: A method of an aspect is performed by a processor. The method includes receiving a partial width load instruction. The partial width load instruction indicates a memory location of a memory as a source operand and indicates a register as a destination operand. The method includes loading data from the indicated memory location to the processor in response to the partial width load instruction. The method includes writing at least a portion of the loaded data to a partial width of the register in response to the partial width load instruction. The method includes finishing writing the register with a set of bits stored in a remaining width of the register that have bit values that depend on a partial width load mode of the processor. The partial width load instruction does not indicate the partial width load mode. Other methods, processors, and systems are also disclosed.

Abstract translation: 一个方面的方法是通过一个处理器来执行。 该方法包括接收部分宽度加载指令。 部分宽度负载指令指示存储器作为源操作数的存储器位置和指示寄存器作为目标操作数。 该方法包括响应于该部分宽度加载指令从所指示的存储器位置到所述处理器加载数据。 该方法包括：响应于所述部分宽度加载指令写入至少所述加载的数据到寄存器的局部宽度的部分。 该方法包括：精加工用一组存储在寄存器thathave比特值的剩余宽度也依赖于处理器的局部宽度负载模式位的写寄存器。 部分宽度加载指令不指示部分宽度负载模式。 因此其他方法，处理器和系统是游离缺失盘。

公开(公告)号：EP3014424A4

公开(公告)日：2017-03-01

申请号：EP14818771

申请日：2014-06-12

Applicant: INTEL CORP

Inventor： DIXON MARTIN G ,  RASH WILLIAM C ,  SANTIAGO YAZMIN A

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/3855 ,  G06F9/3891

Abstract: A processor of an aspect includes an instruction fetch unit to fetch a pair of instruction order enforcement instructions. The pair of instruction order enforcement instructions are part of an instruction set of the processor. The pair of instruction order enforcement instructions includes an activation instruction and an enforcement instruction. The activation instruction is to occur before the enforcement instruction in a program order. The processor also includes an instruction order enforcement module. The instruction order enforcement module, in response to the pair of the instruction order enforcement instructions, is to prevent instructions occurring after the enforcement instruction in the program order, from being processed prior to the activation instruction, in an out-of-order portion of the processor. Other processors are also disclosed, as are various methods, systems, and instructions.

Abstract translation: 一个形态的处理器包括取指令单元获取一个对指令顺序执行指令。 在对指令顺序执行指令集的处理器的指令的一部分。 在对指令顺序执行的指令包括指令和执法指令激活。 激活指令在程序顺序执行指令之前发生。 因此，该处理器包括：为了执行模块上的指令。 指令顺序执行模块，响应于所述对的指令顺序执行指令，是为了防止，从之前的激活指令在的乱序部分被处理，按照程序顺序执行指令之后发生指令 处理器。 其他处理器使游离缺失盘，因为有各种方法，系统和指令。

公开(公告)号：BR102014006021A2

公开(公告)日：2015-10-20

申请号：BR102014006021

申请日：2014-03-14

Applicant: INTEL CORP

Inventor： DIXON MARTIN G ,  RASH WILLIAM C ,  SANTIAGO YAZMIN A

IPC: G06F9/30 ,  G06F12/08 ,  G06F12/14

Abstract: processadores, métodos e sistemas para relaxamento de sincronização de acesso á memória compartilhada. a presente invenção, em um aspecto, tratade um processador que inclui uma pluralidade de processadores lógicos. um primeiro processador lógico da pluralidade de processadores deve executar software que inclui uma instrução de sincronização de acesso à memória que deve sincronizar acessos a uma memória, o processador também inclui lógica de relaxamento de sincronização de acesso à memória que deve impedir que a instrução de sincronização de acesso à memória sincronize acessos à memória quando o processador estiver em um modo relaxado de sincronização de acesso à memória.,

公开(公告)号：GB2513975A

公开(公告)日：2014-11-12

申请号：GB201404224

申请日：2014-03-11

Applicant: INTEL CORP

Inventor： RASH WILLIAM C ,  DIXON MARTIN G

IPC: G06F9/30

Abstract: A processor 101 includes decode logic 105 to receive and decode instructions 103 including logic 119 to determine when the received instructions are emulated instructions 104 and initiate emulation of those instructions such as by emulation logic 117 or emulation software 113. The processor may also include an emulation mode 118 setting in a configuration register and an emulation mode aware post-decode instruction processor logic 120 coupled with the decode logic and emulation logic. Emulation of an instruction may generate a set of one or more instructions in the same instruction set as the first instruction to provide support for otherwise unsupported instructions, legacy instructions or deprecated instructions. Complex instructions may be emulated using a set of simpler instructions which can be from a different instruction sets or may even be from the same instruction set. The determination of whether an instruction is to be emulated can involve examining metadata of a software module including the instruction and in turn the storing of emulation mode 116 in the configuration register.