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    Mechanism to schedule thread on os-sequestered sequencer without operating system intervention
    2.
    发明专利
    Mechanism to schedule thread on os-sequestered sequencer without operating system intervention 审中-公开
    在没有操作系统干预的情况下在OS-序列测序仪上安排螺线的机制

    公开(公告)号：JP2011076639A

    公开(公告)日：2011-04-14

    申请号：JP2011007496

    申请日：2011-01-18

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： BIGBEE BRYANT ,  HANKINS RICHARD A ,  WANG HONG ,  DIEP TRUNG ,  XINMIN TIAN ,  KAUSHIK CHIV ,  SHEN JOHN ,  MALLICK ASIT ,  GIRKAR MILLIND ,  SETHI PRASHANT ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  HELD JAMES PAUL

    IPC: G06F9/46

    CPC classification number: G06F9/4843

    Abstract: PROBLEM TO BE SOLVED: To provide a method, apparatus and system for scheduling OS-independent 'shreds' without intervention of an operating system.
    SOLUTION: For at least in one embodiment, the shred is scheduled for execution by a scheduler routine rather than the operating system. The scheduler routine may run on each enabled sequencer. The schedulers may retrieve shred descriptors from a queue system. The sequencer associated with the scheduler may then execute the shred described by the descriptor. Other embodiments are also described and claimed.
    COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于在不介入操作系统的情况下调度与OS无关的“碎片”的方法，装置和系统。 解决方案：至少在一个实施例中，碎片被调度为由调度器例程而不是操作系统执行。 调度程序例程可以在每个启用的定序器上运行。 调度器可以从队列系统检索碎片描述符。 与调度器相关联的定序器然后可以执行由描述符描述的碎片。 还描述和要求保护其他实施例。 版权所有（C）2011，JPO＆INPIT

    Mechanism for scheduling thread on os isolated sequencer without interposition of operating system
    3.
    发明专利
    Mechanism for scheduling thread on os isolated sequencer without interposition of operating system 有权
    用于在没有操作系统中断的操作系统分离序列上安排螺纹的机构

    公开(公告)号：JP2013191244A

    公开(公告)日：2013-09-26

    申请号：JP2013140714

    申请日：2013-07-04

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： BIGBEE BRYANT ,  HANKINS RICHARD A ,  WANG HONG ,  DIEP TRUNG ,  XINMIN TIAN ,  KAUSHIK CHIV ,  JOHN SHEN ,  MALLICK ASIT ,  GIRKAR MILLIND ,  SETHI PRASHANT ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  HELD JAMES PAUL

    IPC: G06F9/46

    CPC classification number: G06F9/4843

    Abstract: PROBLEM TO BE SOLVED: To provide various embodiments of a method, a device and a system for scheduling OS independent 'shred' without interposition of an operating system.SOLUTION: For at least one embodiment, a shred is scheduled for execution not by an operating system but by a scheduler routine. The scheduler routine can travel on the respective validated sequencers. A scheduler can acquire a shred descriptor from a queue system. Next, a sequencer associated with the scheduler can execute the shred to be described by the descriptor. Other embodiments are also described, and claimed.

    Abstract translation: 要解决的问题：提供方法，设备和系统的各种实施例，用于在不插入操作系统的情况下调度独立于OS的“独立”操作系统。解决方案：对于至少一个实施例，碎片被安排执行而不是通过操作 系统，但通过调度程序。 调度程序可以在相应的经过验证的定序器上运行。 调度程序可以从队列系统中获取碎片描述符。 接下来，与调度器相关联的定序器可以执行由描述符描述的细丝。 还描述和要求保护其他实施例。

    Apparatus, system, and method for persistent user-level thread
    4.
    发明专利
    Apparatus, system, and method for persistent user-level thread 有权
    用于用户级螺纹的装置，系统和方法

    公开(公告)号：JP2007102781A

    公开(公告)日：2007-04-19

    申请号：JP2006266590

    申请日：2006-09-29

    Applicant: Intel Corp ,  インテル・コーポレーション

    Inventor： CHINYA GAUTHAM ,  WANG HONG ,  SETHI PRASHANT ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEN JOHN ,  HANKINS RICHARD ,  ZOU XIANG ,  PATEL BAIJU ,  BRANDT JASON ,  AGGARWAL ANIL ,  REID JOHN

    IPC: G06F9/50 ,  G06F9/48

    CPC classification number: G06F9/3005 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3877 ,  G06F9/3885 ,  G06F9/461

    Abstract: PROBLEM TO BE SOLVED: To provide a method for generating a persistent user-level thread.
    SOLUTION: Embodiments of the invention provide a method of creating, based on an operating-system (OS)-scheduled thread running on an OS-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an OS-sequestered sequencer independently of context switch activities on the OS-scheduled thread. The OS-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional OS-visible sequencer to provide OS services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
    COPYRIGHT: (C)2007,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于生成持久用户级线程的方法。 解决方案：本发明的实施例提供了一种基于在OS可见定序器上运行并使用指令集扩展的操作系统（OS）调度的线程来创建持久的用户级线程来运行的方法 独立于操作系统调度的线程上的上下文切换活动的OS隔离的定序器。 OS调度的线程和持久用户级线程可以共享公共的虚拟地址空间。 本发明的实施例还可以提供一种使服务线程在附加的OS可见定序器上运行以向持久用户级线程提供OS服务的方法。 本发明的实施例还可以提供其装置，系统和机器可读介质。 版权所有（C）2007，JPO＆INPIT

    Instruction set architecture-based inter-sequencer communication with heterogeneous resource
    5.
    发明专利
    Instruction set architecture-based inter-sequencer communication with heterogeneous resource 审中-公开
    具有异构资源的基于指令集架构的串行间通信

    公开(公告)号：JP2011146077A

    公开(公告)日：2011-07-28

    申请号：JP2011101385

    申请日：2011-04-28

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： WANG HONG ,  SHEN JOHN ,  ZHANG HONG ,  HANKINS RICHARD ,  HAMMARLUND PER ,  RODGERS DION ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEAFFER GAD ,  TALGAM YOAV ,  YOSEF YUVAL ,  HELD JAMES P

    IPC: G06F9/38

    CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06T1/20

    Abstract: PROBLEM TO BE SOLVED: To provide a method, a device, and a system for performing effective communication between instruction set architecture-based sequencers having heterogeneous resources. SOLUTION: The method includes: a step in which a first instruction sequencer is connected from a user-level application via the first instruction sequencer and a request is directly communicated to an accelerator having a heterogeneous resource with respect to the instruction sequencer; a step of providing the accelerator with the request via an exoskeleton related to the accelerator; and a step of performing a first function in parallel to a second function in the first instruction sequencer in response to the request in the accelerator. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于在具有异构资源的指令集体系结构的定序器之间执行有效通信的方法，设备和系统。 该方法包括：第一指令定序器经由第一指令定序器从用户级应用连接并且请求直接传送到相对于指令定序器具有异构资源的加速器的步骤; 通过与加速器有关的外骨骼提供加速器请求的步骤; 以及响应于加速器中的请求，在第一指令定序器中执行与第二功能并行的第一功能的步骤。 版权所有（C）2011，JPO＆INPIT

    9.
    发明专利
    未知

    公开(公告)号：DE112006000807T5

    公开(公告)日：2008-01-31

    申请号：DE112006000807

    申请日：2006-04-05

    Applicant: INTEL CORP

    Inventor： WANG HONG ,  CHINYA GAUTHAM ,  HANKINS RICHARD ,  RAKVIC RYAN ,  SHEN JOHN ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  HAMMARLUND PER ,  ZOU XIANG ,  BRANDT JASON ,  SETHI PRASHANT ,  REID JOHN ,  POULSEN DAVID ,  RODGERS SCOTT ,  CARMEAN DOUGLAS ,  PATEL BAIJU ,  SHAH SANJIV ,  HELD JAMES ,  ABEL JAMES

    IPC: G06F9/38

    Abstract: Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

    INTEGRITÄTSSCHUTZ MIT GERINGEM OVERHEAD UND HOHER VERFÜGBARKEIT FÜR VERTRAUENSDOMÄNEN
    10.
    发明专利
    INTEGRITÄTSSCHUTZ MIT GERINGEM OVERHEAD UND HOHER VERFÜGBARKEIT FÜR VERTRAUENSDOMÄNEN 未知

    公开(公告)号：DE102019110309A1

    公开(公告)日：2020-01-02

    申请号：DE102019110309

    申请日：2019-04-18

    Applicant: INTEL CORP

    Inventor： PATEL BAIJU ,  YAP KIRK ,  CHHABRA SIDDHARTHA ,  AGARWAL RAJAT

    IPC: G06F12/14 ,  G06F21/50

    Abstract: Es werden Techniken beschrieben, um eine kryptografische Speicherisolierung mit geringem Overhead bereitzustellen, um Angriffsschwachstellen in einer virtualisierten Mehrbenutzer-Rechenumgebung zu mindern. Speicherlese- und Speicherschreiboperationen für Zieldaten, wobei jede Operation über einen Befehl initiiert wird, der mit einer bestimmten virtuellen Maschine (VM) assoziiert ist, schließen die Generierung und/oder Validierung eines Nachrichtenauthentifizierungscodes ein, der wenigstens auf einem VM-spezifischen kryptografischen Schlüssel und einer physikalischen Speicheradresse der Zieldaten basiert. Derartige Operationen können ferner das Senden des generierten Nachrichtenauthentifizierungscodes über eine Vielzahl von Zusatzbits beinhalten, die innerhalb einer Datenzeile integriert sind, die die Zieldaten einschließt. Im Falle eines Validierungsfehlers können ein oder mehrere Fehlercodes generiert und verschiedenen Entitäten der Vertrauensdomänenarchitektur basierend auf einem Betriebsmodus der assoziierten virtuellen Maschine bereitgestellt werden.

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