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公开(公告)号:BR9610095A
公开(公告)日:1999-02-17
申请号:BR9610095
申请日:1996-07-17
Applicant: INTEL CORP
Inventor: WITT WOLF , MENNEMEIR LARRY M , KOWASHI EEICHI , PELEG ALEXANDER D , DULONG CAROLE , GLEW ANDREW F , MITTAL MILLIND , EITAN BENNY , YAARI YAACOV
IPC: G06F5/00 , G06F7/544 , G06F7/57 , G06F7/60 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/38 , G06F15/78 , G06F7/00 , G06F7/38 , G06F7/52 , G06F7/50
Abstract: An apparatus comprising: a first storage area operable to have stored therein a first packed data containing at least an A 1 , an A 2 , an A 3 , and an A 4 element; a second storage area operable to have stored therein a second packed data containing at least a B 1 , a B 2 , a B 3 , and a B 4 element; a multiply circuit including a first multiplier coupled to said first storage area to receive said A 1 and coupled to said second storage area to receive said B 1 ; a second multiplier coupled to said first storage area to receive said A 2 and coupled to said second storage are to receive said B 2 ; a third multiplier coupled to said first storage area to receive said A 3 and coupled to said second storage area to receive said B 3 ; a fourth multiplier coupled to said first storage area to receive said A 4 and coupled to said second storage area to receive said B 4 ; a first adder coupled to said first multiplier and said second multiplier; a second adder coupled to said third multiplier and said fourth multiplier; and a third storage area coupled to said first adder and said second adder, said third storage area having at least a first field and a second field, said first field for saving an output of said first adder as a first data element of a third packed data, said second field for saving an output of said second adder as a second data element of said third packed data.
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公开(公告)号:AU6677896A
公开(公告)日:1997-03-19
申请号:AU6677896
申请日:1996-07-17
Applicant: INTEL CORP
Inventor: PELEG ALEXANDER D , YAARI YAACOV , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY , GLEW ANDREW F , DULONG CAROLE , KOWASHI EIICHI , WITT WOLF
IPC: G06F5/00 , G06F7/544 , G06F7/57 , G06F7/60 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/38 , G06F15/78 , G06F7/00 , G06F7/38 , G06F7/52 , G06F7/50
Abstract: An apparatus comprising: a first storage area operable to have stored therein a first packed data containing at least an A 1 , an A 2 , an A 3 , and an A 4 element; a second storage area operable to have stored therein a second packed data containing at least a B 1 , a B 2 , a B 3 , and a B 4 element; a multiply circuit including a first multiplier coupled to said first storage area to receive said A 1 and coupled to said second storage area to receive said B 1 ; a second multiplier coupled to said first storage area to receive said A 2 and coupled to said second storage are to receive said B 2 ; a third multiplier coupled to said first storage area to receive said A 3 and coupled to said second storage area to receive said B 3 ; a fourth multiplier coupled to said first storage area to receive said A 4 and coupled to said second storage area to receive said B 4 ; a first adder coupled to said first multiplier and said second multiplier; a second adder coupled to said third multiplier and said fourth multiplier; and a third storage area coupled to said first adder and said second adder, said third storage area having at least a first field and a second field, said first field for saving an output of said first adder as a first data element of a third packed data, said second field for saving an output of said second adder as a second data element of said third packed data.
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公开(公告)号:HK1099095A1
公开(公告)日:2007-08-03
申请号:HK07105278
申请日:2007-05-18
Applicant: INTEL CORP
Inventor: PELEG ALEXANDER D , YAARI YAACOV , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY , GLEW ANDREW F , DULONG CAROLE , KOWASHI EIICHI , WITT WOLF
IPC: G06F20060101 , G06F5/00 , G06F7/544 , G06F7/57 , G06F7/60 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/38 , G06F15/78
Abstract: An apparatus comprising: a first storage area operable to have stored therein a first packed data containing at least an A 1 , an A 2 , an A 3 , and an A 4 element; a second storage area operable to have stored therein a second packed data containing at least a B 1 , a B 2 , a B 3 , and a B 4 element; a multiply circuit including a first multiplier coupled to said first storage area to receive said A 1 and coupled to said second storage area to receive said B 1 ; a second multiplier coupled to said first storage area to receive said A 2 and coupled to said second storage are to receive said B 2 ; a third multiplier coupled to said first storage area to receive said A 3 and coupled to said second storage area to receive said B 3 ; a fourth multiplier coupled to said first storage area to receive said A 4 and coupled to said second storage area to receive said B 4 ; a first adder coupled to said first multiplier and said second multiplier; a second adder coupled to said third multiplier and said fourth multiplier; and a third storage area coupled to said first adder and said second adder, said third storage area having at least a first field and a second field, said first field for saving an output of said first adder as a first data element of a third packed data, said second field for saving an output of said second adder as a second data element of said third packed data.
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公开(公告)号:EP0847551A4
公开(公告)日:2001-11-21
申请号:EP96926742
申请日:1996-07-17
Applicant: INTEL CORP
Inventor: PELEG ALEXANDER D , YAARI YAACOV , MITTAL MILLIND , MENNEMEIER LARRY M , EITAN BENNY , GLEW ANDREW F , DULONG CAROLE , KOWASHI EIICHI , WITT WOLF
IPC: G06F5/00 , G06F7/544 , G06F7/57 , G06F7/60 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/38 , G06F15/78 , G06F7/00 , G06F7/02 , G06F7/38 , G06F7/50 , G06F7/52
CPC classification number: G06F7/57 , G06F7/49921 , G06F7/49994 , G06F7/5443 , G06F7/607 , G06F9/30014 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30109 , G06F9/30112 , G06F9/3013 , G06F17/10 , G06F17/147 , G06F2207/382 , G06F2207/3828
Abstract: An apparatus for including in a processor a set of instructions that support operations on packed data required by typical multimedia applications. In one embodiment, the invention includes a processor having a storage area (150), a decoder (165), and a plurality of circuits (130). The plurality of circuits provide for the execution of a number of instructions to manipulate packed data. In this embodiment, these instructions include pack, unpack, packed multiply, packed add, packed subtract, packed compare, and packed shift.
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