公开(公告)号：BR9610095A

公开(公告)日：1999-02-17

申请号：BR9610095

申请日：1996-07-17

Applicant: INTEL CORP

Inventor： WITT WOLF ,  MENNEMEIR LARRY M ,  KOWASHI EEICHI ,  PELEG ALEXANDER D ,  DULONG CAROLE ,  GLEW ANDREW F ,  MITTAL MILLIND ,  EITAN BENNY ,  YAARI YAACOV

IPC: G06F5/00 ,  G06F7/544 ,  G06F7/57 ,  G06F7/60 ,  G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F9/38 ,  G06F15/78 ,  G06F7/00 ,  G06F7/38 ,  G06F7/52 ,  G06F7/50

Abstract: An apparatus comprising: a first storage area operable to have stored therein a first packed data containing at least an A 1 , an A 2 , an A 3 , and an A 4 element; a second storage area operable to have stored therein a second packed data containing at least a B 1 , a B 2 , a B 3 , and a B 4 element; a multiply circuit including a first multiplier coupled to said first storage area to receive said A 1 and coupled to said second storage area to receive said B 1 ; a second multiplier coupled to said first storage area to receive said A 2 and coupled to said second storage are to receive said B 2 ; a third multiplier coupled to said first storage area to receive said A 3 and coupled to said second storage area to receive said B 3 ; a fourth multiplier coupled to said first storage area to receive said A 4 and coupled to said second storage area to receive said B 4 ; a first adder coupled to said first multiplier and said second multiplier; a second adder coupled to said third multiplier and said fourth multiplier; and a third storage area coupled to said first adder and said second adder, said third storage area having at least a first field and a second field, said first field for saving an output of said first adder as a first data element of a third packed data, said second field for saving an output of said second adder as a second data element of said third packed data.

公开(公告)号：BR9509845A

公开(公告)日：1997-12-30

申请号：BR9509845

申请日：1995-12-01

Applicant: INTEL CORP

Inventor： PELEG ALEXANDER ,  YAARI YAAKOW ,  MITTAL MILIND ,  MENNEMEIR LARRY M ,  EITAN BENNY

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F9/318 ,  G06F7/14

Abstract: A processor includes a first register (209) for storing a first packed data, a decoder (202), and a functional unit (203). The decoder has a control signal input (207) for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation, and the second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder (202) and the register (209). The functional unit performs the pack operation and the unpack operation using the first packed data as well as move operation.