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    소스 페르미 필터 전계 효과 트랜지스터
    2.
    发明公开
    소스 페르미 필터 전계 효과 트랜지스터 审中-公开
    源费米滤波器场效应晶体管

    公开(公告)号：KR20180019074A

    公开(公告)日：2018-02-23

    申请号：KR20177033337

    申请日：2015-06-22

    Applicant: INTEL CORP

    Inventor： AVCI UYGAR E ,  YOUNG IAN A

    IPC: H01L29/78 ,  H01L29/417 ,  H01L29/73

    CPC classification number: H01L29/78

    Abstract: 소스와소스콘택트사이에페르미필터를갖는페르미필터전계효과트랜지스터들, 그러한트랜지스터들을포함하는시스템들, 및그것들을형성하는방법들이논의된다. 그러한트랜지스터들은둘 다제1 극성을갖는소스와드레인사이의채널및 페르미필터가제1 극성에상보적인제2 극성을갖도록소스와소스콘택트사이의페르미필터를포함할수 있다.

    Abstract translation: 讨论了在源极和源极触点之间具有费米滤波器的费米滤波器场效应晶体管，包括这种晶体管的系统以及形成它们的方法。 这种晶体管具有与源极和具有两个多药第一极性的第一极性可包含在源极和源极触点之间的费米过滤器的漏极之间的沟道和费米滤波器互补的第二极性。

    핀 간 부동 게이트 디바이스를 갖는 반휘발성 내장형 메모리 및 방법
    3.
    发明公开
    핀 간 부동 게이트 디바이스를 갖는 반휘발성 내장형 메모리 및 방법 审中-公开
    半易失性嵌入式存储器和具有引脚间浮动门器件的方法

    公开(公告)号：KR20180020263A

    公开(公告)日：2018-02-27

    申请号：KR20187002079

    申请日：2015-06-26

    Applicant: INTEL CORP

    Inventor： AVCI UYGAR E ,  MORRIS DANIEL H ,  YOUNG IAN A ,  RAMEY STEPHEN M

    IPC: H01L27/11521 ,  H01L27/11519 ,  H01L27/11558 ,  H01L29/788

    CPC classification number: H01L29/78 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/7881

    Abstract: 본개시내용의실시예들은핀 간부동게이트들을갖는반휘발성내장형메모리를위한기술들및 구성들을제공한다. 일실시예에서, 장치는반도체기판; 및반도체기판상에형성되고비트셀을포함하는부동게이트메모리구조물을포함하고, 비트셀은기판으로부터연장되는제1, 제2, 및제3 핀구조물; 제1 핀구조물과제2 핀구조물사이, 및제2 핀구조물과제3 핀구조물사이에배치된산화물층; 산화물층 상에배치되고, 제1 핀구조물의최상부와연결되며제1 핀구조물의최상부위쪽에연장되는제1 트랜지스터의게이트; 및제2 핀구조물과제3 핀구조물사이의산화물층 상에배치되는제2 트랜지스터의부동게이트를포함한다. 다른실시예들이설명및/또는청구될수 있다.

    Abstract translation: 本公开的实施例提供用于具有钉扎栅极门的半易失性嵌入式存储器的技术和配置。 在一个实施例中，该设备包括半导体衬底; 以及形成在半导体衬底上并包括位单元的浮栅存储结构，位单元包括从衬底延伸的第一，第二和第三引脚结构; 第一引脚结构任务在两个引脚结构之间设置氧化层，以及在三引脚结构之间设置第二引脚结构任务; 第一晶体管的栅极，设置在氧化物层上并连接到第一鳍状结构的顶部并且在第一鳍状结构的顶部上方延伸; 并且在双引脚结构任务和三引脚结构之间的氧化物层上设置第二晶体管的浮动栅极。 其他实施例可以被描述和/或要求保护。

    SPIN-ORBIT LOGIC WITH CHARGE INTERCONNECTS AND MAGNETOELECTRIC NODES
    6.
    发明申请
    SPIN-ORBIT LOGIC WITH CHARGE INTERCONNECTS AND MAGNETOELECTRIC NODES 审中-公开
    带有电荷互连和磁电节点的自旋轨道逻辑

    公开(公告)号：WO2016105436A8

    公开(公告)日：2017-05-26

    申请号：PCT/US2014072447

    申请日：2014-12-26

    Applicant: INTEL CORP

    Inventor： MANIPATRUNI SASIKANTH ,  NIKONOV DMITRI E ,  YOUNG IAN A

    IPC: H01L43/02

    CPC classification number: H01L27/22 ,  H01L27/228 ,  H01L43/08 ,  H03K19/173 ,  H03K19/18

    Abstract: An apparatus including a spin to charge conversion node; and a charge to spin conversion node, wherein an input to the spin to charge conversion node produces an output at the charge to spin conversion node. An apparatus including a magnet including an input node and output node, the input node including a capacitor operable to generate magnetic response in the magnet and the output node including at least one spin to charge conversion material. A method including injecting a spin current from a first magnet; converting the spin current into a charge current operable to produce a magnetoelectric interaction with a second magnet; and changing a direction of magnetization of the second magnet in response to the magnetoelectric interaction. A method including injecting a spin current from an input node of a magnet; and converting the spin current into a charge current at an output node of the magnet.

    Abstract translation: 包括自旋至电荷转换节点的设备; 以及对自旋转换节点的电荷，其中自旋到电荷转换节点的输入在自旋转换节点的电荷处产生输出。 一种包括磁体的设备，所述磁体包括输入节点和输出节点，所述输入节点包括可操作以在所述磁体中产生磁响应的电容器，并且所述输出节点包括至少一个自旋转电荷转换材料。 一种方法，包括从第一磁体注入自旋电流; 将所述自旋电流转换成可操作以与第二磁体产生磁电相互作用的充电电流; 以及响应于磁电相互作用而改变第二磁体的磁化方向。 一种方法，包括从磁体的输入节点注入自旋电流; 以及将自旋电流转换成磁体的输出节点处的充电电流。

    PHASE INTERPOLATOR
    7.
    发明申请
    PHASE INTERPOLATOR 审中-公开
    相位插补器

    公开(公告)号：WO2007075312A3

    公开(公告)日：2008-04-03

    申请号：PCT/US2006047110

    申请日：2006-12-08

    Applicant: INTEL CORP ,  FAN YONGPING ,  YOUNG IAN A

    Inventor： FAN YONGPING ,  YOUNG IAN A

    IPC: H03H11/16 ,  H03K5/13 ,  H04L7/033

    CPC classification number: H03H11/16 ,  H04L7/0338

    Abstract: A phase interpolator includes a first circuit to generate a first signal (PHINO) having a first phase delay and a second signal (PHINl) having a second phase delay and a phase mixer (105). The phase mixer (105) is coupled to receive the first and second signals from the first circuit. The phase mixer (105) includes multiple current drivers (510) each including a current driver input coupled to selectively delay one of the first or second signals and a current driver output coupled to output a phase delayed signal. The current driver outputs (01) of the current drivers (510) are coupled together to combine the phase delayed signals from the current drivers to generate an output phase delayed signal having a phase interpolated from the first (PHINO) and second signals. (phinl)

    Abstract translation: 相位内插器包括产生具有第一相位延迟的第一信号（PHINO）和具有第二相位延迟的第二信号（PHIN1）和相位混频器（105）的第一电路。 相位混合器（105）被耦合以从第一电路接收第一和第二信号。 相位混合器（105）包括多个电流驱动器（510），每个电流驱动器包括耦合以选择性地延迟第一或第二信号中的一个的电流驱动器输入和耦合以输出相位延迟信号的电流驱动器输出。 当前驱动器（510）的当前驱动器输出（01）被耦合在一起以组合来自当前驱动器的相位延迟信号，以产生具有从第一（PHINO）和第二信号内插的相位的输出相位延迟信号。 （phinl）

    APPARATUSES, METHODS, AND SYSTEMS FOR DENSE CIRCUITRY USING TUNNEL FIELD EFFECT TRANSISTORS
    8.
    发明公开
    APPARATUSES, METHODS, AND SYSTEMS FOR DENSE CIRCUITRY USING TUNNEL FIELD EFFECT TRANSISTORS 审中-公开

    公开(公告)号：EP3235133A4

    公开(公告)日：2018-08-01

    申请号：EP15870554

    申请日：2015-11-11

    Applicant: INTEL CORP

    Inventor： MORRIS DANIEL H ,  AVCI UYGAR E ,  RIOS RAFAEL ,  YOUNG IAN A

    IPC: H03K19/0185

    CPC classification number: G11C11/419 ,  G11C5/145 ,  G11C11/412 ,  H01L27/1104 ,  H03K3/356104

    Abstract: Embodiments include apparatuses, methods, and systems for a circuit to shift a voltage level. The circuit may include a first inverter that includes a first transistor coupled to pass a low voltage signal and a second inverter coupled to receive the low voltage signal. The circuit may further include a second transistor coupled to receive the low voltage signal from the second inverter to serve as a feedback device and produce a high voltage signal. In embodiments, the first transistor conducts asymmetrically to prevent crossover of the high voltage signal into the low voltage domain. A low voltage memory array is also described. In embodiments, the circuit to shift a voltage level may assist communication between a logic component including the low voltage memory array of a low voltage domain and a logic component of a high voltage domain. Additional embodiments may also be described.

    APPARATUS AND METHOD TO OPTIMIZE STT-MRAM SIZE AND WRITE ERROR RATE
    10.
    发明公开
    APPARATUS AND METHOD TO OPTIMIZE STT-MRAM SIZE AND WRITE ERROR RATE 审中-公开
    VORRICHTUNG UND VERFAHREN ZUR OPTIMIERUNG DER STT-MRAM-GRÖSSEUND SCHREIBFEHLERRATE

    公开(公告)号：EP3050059A4

    公开(公告)日：2017-04-26

    申请号：EP13894603

    申请日：2013-09-27

    Applicant: INTEL CORP

    Inventor： MANIPATRUNI SASIKANTH ,  NIKONOV DMITRI E ,  YOUNG IAN A

    IPC: G11C11/16 ,  G11C7/12

    CPC classification number: G11C13/0069 ,  G11C7/12 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/5607 ,  G11C2213/79 ,  G11C2213/82

    Abstract: Described is an apparatus comprising: a first select-line; a second select-line; a bit-line; a first bit-cell including a resistive memory element and a transistor, the first bit-cell coupled to the first select-line and the bit-line; a buffer with an input coupled to the first select-line and an output coupled to the second select-line; and a second bit-cell including a resistive memory element and a transistor, the second bit-cell coupled to the second select-line and the bit-line. Described is a magnetic random access memory (MRAM) comprising: a plurality of rows, each row including: a plurality of bit-cells, each bit-cell having an MTJ device coupled to a transistor; and a plurality of buffers, each of which to buffer a select-line signal for a group of bit-cells among the plurality of bit-cells; and a plurality of bit-lines, each row sharing a single bit-line among the plurality of bit-cells in that row.

    Abstract translation: 描述了一种设备，包括：第一选择线; 第二条选择线; 位线; 第一位单元，其包括电阻式存储器元件和晶体管，所述第一位单元耦合到所述第一选择线和所述位线; 缓冲器，具有耦合到所述第一选择线的输入和耦合到所述第二选择线的输出; 以及包括电阻式存储器元件和晶体管的第二位单元，所述第二位单元耦合到所述第二选择线和所述位线。 描述了一种磁性随机存取存储器（MRAM），包括：多行，每行包括：多个位单元，每个位单元具有耦合到晶体管的MTJ器件; 以及多个缓冲器，每个缓冲器缓冲用于所述多个位单元中的一组位单元的选择线信号; 以及多个位线，每行共享该行中的多个位单元之中的单个位线。

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