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    PATCH ON INTERPOSER ARCHITECTURE FOR LOW COST OPTICAL CO-PACKAGING
    3.
    发明申请
    PATCH ON INTERPOSER ARCHITECTURE FOR LOW COST OPTICAL CO-PACKAGING 审中-公开

    公开(公告)号：WO2022139905A1

    公开(公告)日：2022-06-30

    申请号：PCT/US2021/050895

    申请日：2021-09-17

    Applicant: INTEL CORPORATION

    Inventor： LI, Xiaoqian ,  DESHPANDE, Nitin ,  KARHADE, Omkar ,  MAHAJAN, Ravindranath V.

    IPC: H01L25/16 ,  H01L23/36 ,  H01L23/48 ,  H01L23/00

    Abstract: A semiconductor package comprises an interposer and a photonics die. The photonics die has a front side with an on-chip fiber connector and solder bumps, the photonics die over the interposer with the on-chip fiber connector and the solder bumps facing away from the interposer. A patch substrate is mounted on the interposer adjacent to the photonics die. A logic die is mounted on the patch substrate with an overhang past an edge of the patch substrate and the overhang is attached to the solder bumps of the photonics die. An integrated heat spreader (IHS) is over the logic die such that the photonics die does not directly contact the IHS.

    PHOTONIC INTEGRATED CIRCUIT PACKAGING ARCHITECTURES
    5.
    发明申请
    PHOTONIC INTEGRATED CIRCUIT PACKAGING ARCHITECTURES 审中-公开

    公开(公告)号：WO2023048869A1

    公开(公告)日：2023-03-30

    申请号：PCT/US2022/041123

    申请日：2022-08-22

    Applicant: INTEL CORPORATION

    Inventor： LI, Xiaoqian ,  KARHADE, Omkar ,  DESHPANDE, Nitin ,  PIETAMBARAM, Srinivas

    IPC: H01L25/065 ,  H01L23/538 ,  H01L25/18 ,  G02B6/122 ,  H01S5/0239 ,  H01L23/31 ,  H01L25/00 ,  G02B6/12

    Abstract: Microelectronic assemblies including photonic integrated circuits (PICs), related devices and methods, are disclosed herein. For example, in some embodiments, a photonic assembly may include a PIC in a first layer including an insulating material, wherein the PIC has an active side and an opposing backside, and wherein the PIC is embedded in the insulating material with the active side facing up; an optical component optically coupled to the active surface of the PIC and extending at least partially through the first layer; and an integrated circuit (IC) in a second layer, wherein the second layer is on the first layer, wherein the second layer includes the insulating material, wherein the IC is embedded in the insulating material in the second layer, and wherein the IC is electrically coupled to the active side of the PIC.

    THROUGH-MOLD-INTERCONNECT STRUCTURE ON AN IC DIE DIRECTLY BONDED TO ANOTHER IC DIE
    7.
    发明公开
    THROUGH-MOLD-INTERCONNECT STRUCTURE ON AN IC DIE DIRECTLY BONDED TO ANOTHER IC DIE 审中-公开

    公开(公告)号：EP4203005A3

    公开(公告)日：2023-07-05

    申请号：EP22209177.9

    申请日：2022-11-23

    Applicant: INTEL Corporation

    Inventor： MALLIK, Debendra ,  KARHADE, Omkar ,  DESHPANDE, Nitin

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00

    Abstract: An integrated circuit (IC) package comprises a first IC die comprising a first hardware interface at a first side of the first die, and one or more first conductive contacts at the first side. A second IC die coupled to the first die comprises a second hardware interface at a second side of the second die. Second conductive contacts of the first hardware interface are each in direct contact with a respective one of third conductive contacts of the second hardware interface. A third hardware interface comprises: one or more interconnect structures, each coupled to a respective one of the one or more first conductive contacts and each comprising a fourth conductive contact, and fifth conductive contacts at a third side of the second die, wherein the one or more interconnect structures are each to electrically couple the third hardware interface to the first die.

    MICRO-LENS ARRAY OPTICALLY COUPLED WITH A PHOTONICS DIE
    8.
    发明公开
    MICRO-LENS ARRAY OPTICALLY COUPLED WITH A PHOTONICS DIE 审中-公开

    公开(公告)号：EP4020037A1

    公开(公告)日：2022-06-29

    申请号：EP21195459.9

    申请日：2021-09-08

    Applicant: Intel Corporation

    Inventor： LI, Xiaoqian ,  DESHPANDE, Nitin ,  KARHADE, Omkar

    IPC: G02B6/42 ,  G02B6/34 ,  G02B6/30

    Abstract: Embodiments described herein may be related to apparatuses, processes, and techniques for coupling a micro-lens array to a photonics die. In embodiments, this coupling may be performed as an attach at a wafer level. In embodiments, wafer level optical testing of the photonics die with the attached micro-lens array may be tested electrically and optically before the photonics die is assembled into a package, in various configurations. Other embodiments may be described and/or claimed.

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