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公开(公告)号：US09172160B2
公开(公告)日：2015-10-27
申请号：US13801730
申请日：2013-03-13
Applicant: Intel Corporation
Inventor： Joshua D Heppner , Sriram Srinivasan
CPC classification number: H01R12/7076 , G01R1/0433 , G01R1/0466 , G01R1/06727 , G01R1/06733 , G06F1/1613 , H01R12/714 , H01R12/716 , H01R13/2471 , H01R43/205 , H05K1/181 , Y10T29/49204
Abstract: An apparatus includes a plurality of contact elements to provide electrical continuity between an integrated circuit and an electronic subassembly, wherein a contact element includes a spring element and a separate lead element, wherein the spring element is arranged to be substantially vertically slidable over at least a portion of the lead element in response to a force applied to the contact element.
Abstract translation: 一种装置包括多个接触元件，以在集成电路和电子子组件之间提供电连续性，其中接触元件包括弹簧元件和单独的引线元件，其中弹簧元件布置成基本上可垂直滑动至少一个 引导元件的一部分响应于施加到接触元件的力。
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公开(公告)号：US09704811B1
公开(公告)日：2017-07-11
申请号：US14978294
申请日：2015-12-22
Applicant: Intel Corporation
Inventor： Rajendra C. Dias , Joshua D Heppner , Mitul B Modi , Anna M. Prakash
IPC: H01L23/552 , H01L23/495 , H01L23/31 , H01L21/48 , H01L21/56 , H01L21/78
CPC classification number: H01L23/60 , H01L21/4825 , H01L21/56 , H01L21/565 , H01L21/78 , H01L23/3114 , H01L23/3121 , H01L23/49524 , H01L23/552 , H01L24/27 , H01L24/33 , H01L2224/97 , H01L2924/3025
Abstract: An electric device and method of fabrication of that electric device is disclosed. The electric device includes one or more electrical devices attached to a substrate. The electric device further includes one or more grounding pads attached to the substrate. The electric device further includes a perforated conductive material placed on the substrate. The electric device further includes a molding compound deposited to cover the perforated conductive material, the one or more devices, and the one or more grounding pads.
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公开(公告)号：US09635764B2
公开(公告)日：2017-04-25
申请号：US14866648
申请日：2015-09-25
Applicant: Intel Corporation
Inventor： Shipeng Qiu , Shawna Liff , Kayleen L Helms , Joshua D Heppner , Adel Elsherbini , Johanna Swan , Gary M. Barnes
CPC classification number: H05K1/189 , H05K1/0278 , H05K1/028 , H05K1/036 , H05K1/144 , H05K3/0014 , H05K3/22 , H05K3/303 , H05K3/326 , H05K3/361 , H05K2201/0133 , H05K2201/0308 , H05K2201/041 , H05K2201/047 , H05K2201/057 , H05K2201/10007 , H05K2201/10128 , H05K2203/10 , H05K2203/104 , H05K2203/105 , H05K2203/1105 , H05K2203/1194
Abstract: An integrated circuit that includes a substrate having a shape memory material (SMM), the SMM is in a first deformed state and has a first crystallography structure and a first configuration, the SMM is able to be deformed from a first configuration to a second configuration, the SMM changes to a second crystallography structure and deforms back to the first configuration upon receiving energy, the SMM returns to the first crystallography structure upon receiving a different amount of energy; and an electronic component attached to substrate. In other forms, the SMM is in a first deformed state and has a first polymeric conformation and a first configuration, the SMM changes from a first polymeric conformation to a second polymeric conformation and be deformed from a first configuration to a second configuration, the SMM changes returns to the first polymeric conformation and deforms back to the first configuration upon receiving energy.
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公开(公告)号：US09603276B2
公开(公告)日：2017-03-21
申请号：US14583372
申请日：2014-12-26
Applicant: Intel Corporation
Inventor： David J. Llapitan , Jeffory L. Smalley , Gaurav Chawla , Joshua D Heppner , Vijaykumar Krithivasan , Jonathan W. Thibado , Kuang Liu , Gregorio Murtagian
CPC classification number: H05K7/1084
Abstract: Some forms relate to an electronic assembly that includes a plurality of electronic package. The electronic assembly includes a frame and a first electronic package mounted on the frame. The first electronic package includes a first pin grid array. The electronic assembly further includes a second electronic package mounted on the frame. The second electronic package includes a second pin grid array. The electronic assembly further includes an actuation mechanism on the frame. The actuation mechanism is configured to move the first electronic package and the second electronic package relative to the frame during operation of the actuation mechanism.
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公开(公告)号：US20160043488A1
公开(公告)日：2016-02-11
申请号：US14922791
申请日：2015-10-26
Applicant: Intel Corporation
Inventor： Joshua D Heppner , Sriram Srinivasan
CPC classification number: H01R12/7076 , G01R1/0433 , G01R1/0466 , G01R1/06727 , G01R1/06733 , G06F1/1613 , H01R12/714 , H01R12/716 , H01R13/2471 , H01R43/205 , H05K1/181 , Y10T29/49204
Abstract: An apparatus includes a plurality of contact elements to provide electrical continuity between an integrated circuit and an electronic subassembly, wherein a contact element includes a spring element and a separate lead element, wherein the spring element is arranged to be substantially vertically slidable over at least a portion of the lead element in response to a force applied to the contact element.
Abstract translation: 一种装置包括多个接触元件，以在集成电路和电子子组件之间提供电连续性，其中接触元件包括弹簧元件和单独的引线元件，其中弹簧元件布置成基本上可垂直滑动至少一个 引导元件的一部分响应于施加到接触元件的力。
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Patent Agency Ranking
公开(公告)号：US09601848B2
公开(公告)日：2017-03-21
申请号：US14922791
申请日：2015-10-26
Applicant: Intel Corporation
Inventor： Joshua D Heppner , Sriram Srinivasan
IPC: H01R12/00 , H01R12/70 , H01R12/71 , H01R13/24 , G01R1/04 , G06F1/16 , H01R43/20 , H05K1/18 , G01R1/067
CPC classification number: H01R12/7076 , G01R1/0433 , G01R1/0466 , G01R1/06727 , G01R1/06733 , G06F1/1613 , H01R12/714 , H01R12/716 , H01R13/2471 , H01R43/205 , H05K1/181 , Y10T29/49204
Abstract: An apparatus includes a plurality of contact elements to provide electrical continuity between an integrated circuit and an electronic subassembly, wherein a contact element includes a spring element and a separate lead element, wherein the spring element is arranged to be substantially vertically slidable over at least a portion of the lead element in response to a force applied to the contact element.
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公开(公告)号：US09385457B2
公开(公告)日：2016-07-05
申请号：US14563641
申请日：2014-12-08
Applicant: Intel Corporation
Inventor： Gaurav Chawla , Joshua D Heppner , Zhichao Zhang , David J. Llapitan , Vijaykumar Krithivasan
CPC classification number: H01R12/722 , H01L23/34 , H01L2924/0002 , H01R12/7005 , H01R12/71 , H01R12/724 , H01R12/79 , H01R13/114 , H01L2924/00
Abstract: Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.
Abstract translation: 显示连接器和耦合封装和管芯的方法。 所选择的实例包括具有两个或更多台阶的插头和插座，其具有沿梯田提供的触点。 连接器和方法的示例包括其中连接器可用于包括沿衬底耦合的裸片的封装的配置。 在所选择的示例中，散热器耦合在管芯上，并且封装包括在散热器和被配置为接收连接器的基板之间的侧入口，例如通过侧面接入端口的一个或多个插头或插座。
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公开(公告)号：US09017106B2
公开(公告)日：2015-04-28
申请号：US13826393
申请日：2013-03-14
Applicant: Intel Corporation
Inventor： Joshua D Heppner , Gaurav Chawla
CPC classification number: H01R24/86 , H01R12/724 , H01R12/727 , H01R12/79 , H01R24/60 , H01R43/00 , H01R2107/00 , Y10T29/49117
Abstract: This disclosure relates generally to a connector assembly. In various examples, first conductive members are secured with respect to one another and form a first row and second conductive members are secured with respect to one another, a first subset of the second conductive members forming a second row and a second subset of the second conductive members forming a third row, the second and third rows being parallel and stacked with respect to one another and the second and third rows being orthogonal to the first row. Individual ones of the first and second conductive members are arranged to be coupled at a first end to a corresponding one of contacts. Ones of the first conductive members are arranged to be coupled to a corresponding individual one of the second conductive members proximate a second end of each of the first and second conductive members.
Abstract translation: 本公开总体上涉及连接器组件。 在各种示例中，第一导电构件相对于彼此固定并形成第一行，并且第二导电构件相对于彼此固定，第二导电构件的第一子集形成第二行，第二子集的第二导电构件 形成第三排的导电构件，第二和第三排相对于彼此平行和堆叠，第二和第三行与第一行正交。 第一和第二导电构件中的各个被布置成在第一端耦合到对应的一个触点。 第一导电部件的一部分布置成接近靠近第一和第二导电部件的每一个的第二端的相应的单独的一个第二导电部件。
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公开(公告)号：US08961193B2
公开(公告)日：2015-02-24
申请号：US13712166
申请日：2012-12-12
Applicant: Intel Corporation
Inventor： Gaurav Chawla , Vijaykumar Krithivasan , Joshua D Heppner
IPC: H01R24/86
CPC classification number: H01R43/20 , H01R24/86 , H05K7/1084 , Y10T29/4922
Abstract: An apparatus for coupling an integrated circuit to other electronics can include a housing having an exterior and an interior, the exterior having an exterior bottom surface, the interior defined by an interior bottom surface opposite the exterior bottom surface, and at least one sidewall extending away from the interior bottom surface to define an interior shape that is sized to receive the integrated circuit, with the integrated circuit disposed against the interior bottom surface and the at least one sidewall. The example can include a plurality of exterior contacts exposed along the exterior bottom surface in an exterior contact pattern that is generally circular in shape.
Abstract translation: 用于将集成电路耦合到其它电子设备的装置可以包括具有外部和内部的外壳，外部具有外部底部表面，内部由与外部底部表面相对的内部底部表面限定，并且至少一个侧壁延伸远离 从内部底部表面限定尺寸适于接收集成电路的内部形状，其中集成电路抵靠内部底部表面和至少一个侧壁设置。 该示例可以包括沿着外部底部表面暴露的多个外部接触件，外部接触图案通常为圆形形状。
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公开(公告)号：US08905794B2
公开(公告)日：2014-12-09
申请号：US13711187
申请日：2012-12-11
Applicant: Intel Corporation
Inventor： Gaurav Chawla , Joshua D Heppner , Zhichao Zhang , David J. Llapitan , Vijaykumar Krithivasan
CPC classification number: H01R12/722 , H01L23/34 , H01L2924/0002 , H01R12/7005 , H01R12/71 , H01R12/724 , H01R12/79 , H01R13/114 , H01L2924/00
Abstract: Connectors and methods to couple packages and dies are shown. Selected examples include plugs and receptacles having two or more terraces with contacts provided along the terraces. Examples of connectors and methods include configurations where the connector is usable with a package including a die coupled along a substrate. In selected examples a heat sink is coupled over the die, and a package includes a side access port between the heat sink and the substrate configured to receive the connector, such as one or more of a plug or receptacle through the side access port.
Abstract translation: 显示连接器和耦合封装和管芯的方法。 所选择的实例包括具有两个或更多台阶的插头和插座，其具有沿梯田提供的触点。 连接器和方法的示例包括其中连接器可用于包括沿衬底耦合的裸片的封装的配置。 在所选择的示例中，散热器耦合在管芯上，并且封装包括在散热器和被配置为接收连接器的基板之间的侧入口，例如通过侧面接入端口的一个或多个插头或插座。
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