公开(公告)号：US20190213707A1

公开(公告)日：2019-07-11

申请号：US15867688

申请日：2018-01-10

Applicant: Intel Corporation

Inventor： Niranjan Cooray ,  Nicolas Kacevas ,  Altug Koker ,  Parth Damani ,  Satyanarayana Nekkalapu

IPC: G06T1/60 ,  G06F12/1027 ,  G06F12/1009 ,  G06T1/20

Abstract: Embodiments are generally directed to a scalable memory interface for a graphical processor unit. An embodiment of an apparatus includes a graphical processing unit (GPU) including multiple autonomous engines; a common memory interface for the autonomous engines; and a memory management unit for the common memory interface, the memory management unit including multiple engine modules, wherein each of the engine modules includes a translation-lookaside buffer (TLB) that is dedicated to providing address translation for memory requests for a respective autonomous engine of the plurality of autonomous engines, and a TLB miss tracking mechanism that provides tracking for the respective autonomous engine.

公开(公告)号：US10691603B2

公开(公告)日：2020-06-23

申请号：US16023725

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Nicholas Kacevas ,  Niranjan Cooray ,  Parth Damani ,  Pritav Shah

IPC: G06F12/0846 ,  G06F12/0864 ,  G06F12/0842 ,  G06F12/084 ,  G06F12/1027 ,  G06F12/0837 ,  G06F12/0895 ,  G06F12/1036

Abstract: An apparatus to facilitate cache partitioning is disclosed. The apparatus includes a set associative cache to receive access requests from a plurality of agents and partitioning logic to partition the set associative cache by assigning sub-components of a set address to each of the plurality of agents.

公开(公告)号：US20240160478A1

公开(公告)日：2024-05-16

申请号：US17987185

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Jiasheng Chen ,  Chunhui Mei ,  Ben J. Ashbaugh ,  Naveen Matam ,  Joydeep Ray ,  Timothy Bauer ,  Guei-Yuan Lueh ,  Vasanth Ranganathan ,  Prashant Chaudhari ,  Vikranth Vemulapalli ,  Nishanth Reddy Pendluru ,  Piotr Reiter ,  Jain Philip ,  Marek Rudniewski ,  Christopher Spencer ,  Parth Damani ,  Prathamesh Raghunath Shinde ,  John Wiegert ,  Fataneh Ghodrat

IPC: G06F9/50 ,  G06F12/0875

CPC classification number: G06F9/5016 ,  G06F12/0875 ,  G06F2212/452

Abstract: An apparatus to facilitate increasing processing resources in processing cores of a graphics environment is disclosed. The apparatus includes a plurality of processing resources to execute one or more execution threads; a plurality of message arbiter-processing resource (MA-PR) routers, wherein a respective MA-PR router of the plurality of MA-PR routers corresponds to a pair of processing resources of the plurality of processing resources and is to arbitrate routing of a thread control message from a message arbiter between the pair of processing resources; a plurality of local shared cache (LSC) sequencers to provide an interface between at least one LSC of the processing core and the plurality of processing resources; and a plurality of instruction caches (ICs) to store instructions of the one or more execution threads, wherein a respective IC of the plurality of ICs interfaces with a portion of the plurality of processing resources.

公开(公告)号：US10552937B2

公开(公告)日：2020-02-04

申请号：US15867688

申请日：2018-01-10

Applicant: Intel Corporation

Inventor： Niranjan Cooray ,  Nicolas Kacevas ,  Altug Koker ,  Parth Damani ,  Satyanarayana Nekkalapu

IPC: G06T1/60 ,  G06T1/20 ,  G06F12/1027 ,  G06F12/1009

Abstract: Embodiments are generally directed to a scalable memory interface for a graphical processor unit. An embodiment of an apparatus includes a graphical processing unit (GPU) including multiple autonomous engines; a common memory interface for the autonomous engines; and a memory management unit for the common memory interface, the memory management unit including multiple engine modules, wherein each of the engine modules includes a translation-lookaside buffer (TLB) that is dedicated to providing address translation for memory requests for a respective autonomous engine of the plurality of autonomous engines, and a TLB miss tracking mechanism that provides tracking for the respective autonomous engine.

公开(公告)号：US20200004683A1

公开(公告)日：2020-01-02

申请号：US16023725

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Nicolas Kacevas ,  Niranjan Cooray ,  Parth Damani ,  Pritav Shah

IPC: G06F12/0846 ,  G06F12/0864 ,  G06F12/0842 ,  G06F12/0837 ,  G06F12/084 ,  G06F12/1027

Abstract: An apparatus to facilitate cache partitioning is disclosed. The apparatus includes a set associative cache to receive access requests from a plurality of agents and partitioning logic to partition the set associative cache by assigning sub-components of a set address to each of the plurality of agents.