公开(公告)号：US20210233501A1

公开(公告)日：2021-07-29

申请号：US16752427

申请日：2020-01-24

Applicant: Intel Corporation

Inventor： Prashant Chaudhari ,  Arthur Runyan ,  Michael Derr ,  Jonathan Oder

IPC: G09G5/391 ,  G06F1/08 ,  H03C3/09 ,  H03L7/07

Abstract: Upon external display configuration change, a graphics display driver or any suitable hardware or software modifies the clock frequency of the processor core (e.g., graphics processor core) display engine. The graphics display driver or any suitable hardware or software reprograms the core display clock PLL (CDCLK PLL) to a new frequency, without any dead clocks during such frequency change. A divide-by-2 divider changes the frequency of the PLL on the fly or dynamically. The technique may not require the PLL to be turned off and turned back again at all.

公开(公告)号：US11158292B2

公开(公告)日：2021-10-26

申请号：US16752427

申请日：2020-01-24

Applicant: Intel Corporation

Inventor： Prashant Chaudhari ,  Arthur Runyan ,  Michael Derr ,  Jonathan Oder

IPC: G09G5/391 ,  G09G5/36 ,  G06F1/08 ,  H03C3/09 ,  H03L7/07

Abstract: Upon external display configuration change, a graphics display driver or any suitable hardware or software modifies the clock frequency of the processor core (e.g., graphics processor core) display engine. The graphics display driver or any suitable hardware or software reprograms the core display clock PLL (CDCLK PLL) to a new frequency, without any dead clocks during such frequency change. A divide-by-2 divider changes the frequency of the PLL on the fly or dynamically. The technique may not require the PLL to be turned off and turned back again at all.

公开(公告)号：US20190050308A1

公开(公告)日：2019-02-14

申请号：US15857885

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Prashant Chaudhari ,  Michael Derr ,  Gustavo Espinosa ,  Balaji Vembu ,  Richard Shannon ,  Bradley Coffman ,  Daniel Knollmueller

IPC: G06F11/263 ,  G06F11/22

CPC classification number: G06F11/263 ,  G06F11/2205 ,  G06F11/2215 ,  G06F11/2284

Abstract: Systems, apparatuses and methods may provide for technology that detects a startup of a system on chip (SoC) and injects, during the startup, one or more domain startup errors into a plurality of domains on the SoC. Additionally, the technology may determine whether the domain startup error(s) were detected during the startup. In one example, the plurality of domains include one or more fabric interfaces.

公开(公告)号：US20240160478A1

公开(公告)日：2024-05-16

申请号：US17987185

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Jiasheng Chen ,  Chunhui Mei ,  Ben J. Ashbaugh ,  Naveen Matam ,  Joydeep Ray ,  Timothy Bauer ,  Guei-Yuan Lueh ,  Vasanth Ranganathan ,  Prashant Chaudhari ,  Vikranth Vemulapalli ,  Nishanth Reddy Pendluru ,  Piotr Reiter ,  Jain Philip ,  Marek Rudniewski ,  Christopher Spencer ,  Parth Damani ,  Prathamesh Raghunath Shinde ,  John Wiegert ,  Fataneh Ghodrat

IPC: G06F9/50 ,  G06F12/0875

CPC classification number: G06F9/5016 ,  G06F12/0875 ,  G06F2212/452

Abstract: An apparatus to facilitate increasing processing resources in processing cores of a graphics environment is disclosed. The apparatus includes a plurality of processing resources to execute one or more execution threads; a plurality of message arbiter-processing resource (MA-PR) routers, wherein a respective MA-PR router of the plurality of MA-PR routers corresponds to a pair of processing resources of the plurality of processing resources and is to arbitrate routing of a thread control message from a message arbiter between the pair of processing resources; a plurality of local shared cache (LSC) sequencers to provide an interface between at least one LSC of the processing core and the plurality of processing resources; and a plurality of instruction caches (ICs) to store instructions of the one or more execution threads, wherein a respective IC of the plurality of ICs interfaces with a portion of the plurality of processing resources.

公开(公告)号：US10824529B2

公开(公告)日：2020-11-03

申请号：US15857885

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Prashant Chaudhari ,  Michael Derr ,  Gustavo Espinosa ,  Balaji Vembu ,  Richard Shannon ,  Bradley Coffman ,  Daniel Knollmueller

IPC: G06F11/22 ,  G06F11/263

Abstract: Systems, apparatuses and methods may provide for technology that detects a startup of a system on chip (SoC) and injects, during the startup, one or more domain startup errors into a plurality of domains on the SoC. Additionally, the technology may determine whether the domain startup error(s) were detected during the startup. In one example, the plurality of domains include one or more fabric interfaces.