公开(公告)号：US11210094B2

公开(公告)日：2021-12-28

申请号：US16585427

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Michael Cole ,  Alexandr Kurylev ,  Subramaniam Maiyuran ,  Vikranth Vemulapalli ,  Sriharsha Vadlamani ,  Piotr Reiter

IPC: G06F9/38 ,  G06F9/50 ,  G06T1/20 ,  G06F9/30 ,  G06F12/0815 ,  G06F8/41

Abstract: Systems and methods for minimally intrusive instruction pointer-aware processing resource activity profiling are disclosed. In one embodiment, a graphics processor includes a grouping of processing resources and control logic that is associated with the grouping of processing resources. The control logic is configured to sample a state of at least one processing resource of the grouping of processing resources and to determine activity data from the state with the activity data including at least one of stalls and reason counts for stalling activity, instruction types, pipeline utilization, thread utilization, and shader activity.

公开(公告)号：US20240160478A1

公开(公告)日：2024-05-16

申请号：US17987185

申请日：2022-11-15

Applicant: Intel Corporation

Inventor： Jiasheng Chen ,  Chunhui Mei ,  Ben J. Ashbaugh ,  Naveen Matam ,  Joydeep Ray ,  Timothy Bauer ,  Guei-Yuan Lueh ,  Vasanth Ranganathan ,  Prashant Chaudhari ,  Vikranth Vemulapalli ,  Nishanth Reddy Pendluru ,  Piotr Reiter ,  Jain Philip ,  Marek Rudniewski ,  Christopher Spencer ,  Parth Damani ,  Prathamesh Raghunath Shinde ,  John Wiegert ,  Fataneh Ghodrat

IPC: G06F9/50 ,  G06F12/0875

CPC classification number: G06F9/5016 ,  G06F12/0875 ,  G06F2212/452

Abstract: An apparatus to facilitate increasing processing resources in processing cores of a graphics environment is disclosed. The apparatus includes a plurality of processing resources to execute one or more execution threads; a plurality of message arbiter-processing resource (MA-PR) routers, wherein a respective MA-PR router of the plurality of MA-PR routers corresponds to a pair of processing resources of the plurality of processing resources and is to arbitrate routing of a thread control message from a message arbiter between the pair of processing resources; a plurality of local shared cache (LSC) sequencers to provide an interface between at least one LSC of the processing core and the plurality of processing resources; and a plurality of instruction caches (ICs) to store instructions of the one or more execution threads, wherein a respective IC of the plurality of ICs interfaces with a portion of the plurality of processing resources.

公开(公告)号：US20220156068A1

公开(公告)日：2022-05-19

申请号：US17530040

申请日：2021-11-18

Applicant: Intel Corporation

Inventor： Michael Cole ,  Alexandr Kurylev ,  Subramaniam Maiyuran ,  Vikranth Vemulapalli ,  Sriharsha Vadlamani ,  Piotr Reiter

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0815 ,  G06F9/50

Abstract: Systems and methods for minimally intrusive instruction pointer-aware processing resource activity profiling are disclosed. In one embodiment, a graphics processor includes a grouping of processing resources and control logic that is associated with the grouping of processing resources. The control logic is configured to sample a state of at least one processing resource of the grouping of processing resources and to determine activity data from the state with the activity data including at least one of stalls and reason counts for stalling activity, instruction types, pipeline utilization, thread utilization, and shader activity.

公开(公告)号：US20210096855A1

公开(公告)日：2021-04-01

申请号：US16585427

申请日：2019-09-27

Applicant: Intel Corporation

Inventor： Michael Cole ,  Alexandr Kurylev ,  Subramaniam Maiyuran ,  Vikranth Vemulapalli ,  Sriharsha Vadlamani ,  Piotr Reiter

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/0815

Abstract: Systems and methods for minimally intrusive instruction pointer-aware processing resource activity profiling are disclosed. In one embodiment, a graphics processor includes a grouping of processing resources and control logic that is associated with the grouping of processing resources. The control logic is configured to sample a state of at least one processing resource of the grouping of processing resources and to determine activity data from the state with the activity data including at least one of stalls and reason counts for stalling activity, instruction types, pipeline utilization, thread utilization, and shader activity.