公开(公告)号：JPH05210577A

公开(公告)日：1993-08-20

申请号：JP23865192

申请日：1992-09-07

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN KIOU ,  RI MASASUZU ,  BOKU KIYOUMO ,  IN KIYOUCHIN ,  BOKU SHINSHIYU

IPC: G06F12/06 ,  G11C8/12

Abstract: PURPOSE: To provide a semiconductor device in which AN additional outside chip selection controlling circuit is not necessary in order to improve a chip selection terminal and to constitute a simple decoding circuit inside the semiconductor device. CONSTITUTION: A decoding logic circuit 40 equipped with plural chip selection terminal pairs or the like for selecting a single semiconductor element chip corresponding to the logical combination of an extended address is constituted inside the semiconductor element chip or the like. The decoding logic circuit 40 includes inside logic circuits 30 or the like in the same number as that of the selected semiconductor element chips or the like. Also, the decoding logic circuit 40 includes a module selection terminal (cs) for selecting the overall modules. The inside logic circuit 30 includes a first logic designating circuit 10a which maintains a prescribed logical state and a second logical state circuit 10b which maintains the logical state opposite to that of the first logic designating circuit 10a.

公开(公告)号：JPH05188401A

公开(公告)日：1993-07-30

申请号：JP16459592

申请日：1992-06-23

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN TOUKIYUU ,  BOKU GIYONRIYUU ,  BOKU SHINSHIYU ,  BOKU TETSUJIYUN ,  BOKU KIYOUMO

IPC: G02F1/1343 ,  G02F1/1333 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/86 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: PURPOSE: To prevent the degradation in a yield with an increase in size, to lessen the resistance of gate bus lines and to minimize the shorting between wirings from gate insulating films or the intersected parts of the wirings. CONSTITUTION: This process for production includes a stage for producing unit thin-film transistor(TFT) panels on a polyimide supporting base 33 and a stage for aligning and fixing the unit TFT panels in matrix on a glass substrate 17, then electrically connecting and joining the drain bus lines and gate bus lines of the ends of the unit TFT panels to be joined to each other by an ink jet method. The unit TFT panels are constituted by forming gate metals of three layers Cr/Cu/Cr, forming the respective gate bus lines and drain bus lines on the upper and lower surfaces of the polyimide thin films and connecting drain pads and the drain bus lines by a via hole stage.