公开(公告)号：JPH07152052A

公开(公告)日：1995-06-16

申请号：JP21632294

申请日：1994-09-09

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN KOUBAN ,  GO MITSUTATSU ,  BOKU KISEI ,  BOKU SHIYOUDAI

IPC: G02F1/015 ,  G02F1/313

Abstract: PURPOSE: To extremely decrease switching operating currents and to minimize the operating power of an optical switch by maximizing the contact area between front surface electrodes and high-concn. current injecting regions and effectively restraining an injection current. CONSTITUTION: An n-InGaAs cap layer 15 formed on the upper part of a clad layer 13 has groove-shaped etching sections or apertures 25 in such a manner that the current injection area of a reflection surface 102 formed by Zn-diffused regions 18 in the intersected parts of waveguides. The width design of the Zn diffused regions 18 which are the current injection regions is made free by the cap layer 15 having such groove-shaped apertures 25. The contact area of the high-concn. P -InGaAs regions 18 diffused with Zn and the front surface electrodes 16 is made larger on the same plane than the contact area in the case of an ordinary plane, by which ohmic characteristics are improved.

公开(公告)号：JPH05226598A

公开(公告)日：1993-09-03

申请号：JP31476492

申请日：1992-11-25

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： GO MITSUTATSU ,  RI YUUTAKU

IPC: H01L27/14 ,  H01L21/8252 ,  H01L27/095 ,  H01L27/144 ,  H01L31/10 ,  H01L31/105 ,  H01L31/18

Abstract: PURPOSE: To provide a photoelectric integration device for reception and its manufacture by which reception sensitivity, high-speed operation and reliability can be improved, packaging process can be simplified and the manufacturing cost can be reduced. CONSTITUTION: A photoelectric integration device comprises a photosensor and a transistor formed on a substrate. The photosensor comprises an n-type channel layer (n-InGaAs), an etching-blocking layer (u-Inp), and an absorbing layer (u-InGaAs) which are formed as mesa-types on a part of a semi-insulating substrate (S, I-INP) which is etched up to a specified depth. A transistor comprises an n-type channel layer (n-InGaAs), an etching-blocking layer (u-Inp), and a p-type InP layer which are formed as reverse mesa-type on a part of the semi-insulating substrate which is not etched.

公开(公告)号：JPH08162625A

公开(公告)日：1996-06-21

申请号：JP31732594

申请日：1994-12-20

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： GO MITSUTATSU ,  YASU CHIYUUKEN ,  KIN TEISHIYU

IPC: G02B6/12 ,  G02B6/136 ,  H01L25/16 ,  H01L27/15 ,  H01L31/18 ,  H01L33/12 ,  H01L33/30 ,  H01S5/00 ,  H01S5/02 ,  H01S5/026 ,  H01S5/10 ,  H01L33/00

Abstract: PURPOSE: To obtain an optical integrated circuit manufacturing method capable of maximizing current conversion and the efficiency of optical connection simultaneously by a simple process, on the occasion of integrating an optical waveguide and an active photoelement such as an optical amplifier etc., especially, concerning to a manufacturing method for optical integrated circuits, each having a large number of optical elements and optical waveguides integrated on a single chip. CONSTITUTION: Layers 2, 3, 4 to be used for forming active elements (an optical amplifier for example) are provided beforehand on an InP wafer 1. The surfaces vertical to the surface (001) of the said layers 2, 3, 4 are etched. Etching is performed using a dry etching technique such as RIE etching and so on. After the said etching, the core layer 6 and the clad layer 7 of the waveguide are formed by MOCVD (second crystal growth process).