公开(公告)号：JPH08162625A

公开(公告)日：1996-06-21

申请号：JP31732594

申请日：1994-12-20

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： GO MITSUTATSU ,  YASU CHIYUUKEN ,  KIN TEISHIYU

IPC: G02B6/12 ,  G02B6/136 ,  H01L25/16 ,  H01L27/15 ,  H01L31/18 ,  H01L33/12 ,  H01L33/30 ,  H01S5/00 ,  H01S5/02 ,  H01S5/026 ,  H01S5/10 ,  H01L33/00

Abstract: PURPOSE: To obtain an optical integrated circuit manufacturing method capable of maximizing current conversion and the efficiency of optical connection simultaneously by a simple process, on the occasion of integrating an optical waveguide and an active photoelement such as an optical amplifier etc., especially, concerning to a manufacturing method for optical integrated circuits, each having a large number of optical elements and optical waveguides integrated on a single chip. CONSTITUTION: Layers 2, 3, 4 to be used for forming active elements (an optical amplifier for example) are provided beforehand on an InP wafer 1. The surfaces vertical to the surface (001) of the said layers 2, 3, 4 are etched. Etching is performed using a dry etching technique such as RIE etching and so on. After the said etching, the core layer 6 and the clad layer 7 of the waveguide are formed by MOCVD (second crystal growth process).

公开(公告)号：JPH0864907A

公开(公告)日：1996-03-08

申请号：JP19998995

申请日：1995-08-04

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： RI SHIGEKI ,  CHIYOU TOUKUN ,  KIN TEISHIYU ,  BOKU KEIGEN

IPC: H01S5/00 ,  H01S5/20 ,  H01S5/227 ,  H01S5/30 ,  H01S5/343 ,  H01S3/18

Abstract: PROBLEM TO BE SOLVED: To reduce leakage currents from the joint surface between a semiconductor substrate and the first current blocking layer and that due to thyristor structure. SOLUTION: Through a mask 29, a second clad layer 27, an active layer 25, a first clad layer 23, and a semiconductor substrate 21 are etched with a non-selective etching liquid so as to form a truncated cone. Then the layers 27, 23, and 21, except for the active layer 25 are selectively etched so as to accurately expose a crystal plane, in order that a first current blocking layer and a second current blocking layer are formed to cover the entire structure from the upper side surface of the second clad layer 27 to the upper surface of the semiconductor substrate 21.