公开(公告)号：JPH08130310A

公开(公告)日：1996-05-21

申请号：JP30790394

申请日：1994-12-12

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIYOU GENKIYUU ,  KIYOU SEIGEN ,  KIN JIYOKAN ,  YANAGI SHIYOUZEN

IPC: H01L29/78 ,  H01L21/336 ,  H01L27/08 ,  H01L29/10 ,  H01L29/423

Abstract: PURPOSE: To prevent the effect of a short channel that is a problem being generated from a MOS element where the length of a channel becomes short owing to the high integration of an integrated circuit, the increase in resistance of a source and a drain, and the decrease in the reliability of an element due to, for example, the junction breakdown caused by a metal wiring and an electromigration. CONSTITUTION: A gate electrode 9 in a groove form or in other forms is formed between a gate electrode 4 and a source/drain 7 for securing the depth of the junction of the source and drain that are as deep as the depth of the groove. Therefore, by injecting an impurity with a specific concentration below a gate electrode in groove structure and adjusting the concentration of the impurity, electrical characteristics such as a threshold voltage and a leakage current can be adjusted.

公开(公告)号：JPH08162636A

公开(公告)日：1996-06-21

申请号：JP31538894

申请日：1994-12-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIYOU SEIGEN ,  KIYOU GENKIYUU ,  KIN JIYOKAN ,  YANAGI SHIYOUZEN

IPC: H01L21/768 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78

Abstract: PURPOSE: To provide a field-effect element and its electrode forming method capable for forming the electric contacts of an element aligning them automatically, without a contact hole forming process, in a wiring process between electrodes of a kind of silicon, metal or different kinds of metals. CONSTITUTION: Parts of an insulating film 48 on field oxide films 40 and on parts where electrode contacts of wiring electrodes, electrodes of a kind of silicon, electrodes of different kinds of metals are formed are removed, and only parts surrounding the region of a gate electrode, i.e., gate oxide films 48a, 48b are left unremoved. And a substance for wiring electrodes is applied, and the substance is patterned after that and wiring electrodes 49 are formed.

公开(公告)号：JPH0193159A

公开(公告)日：1989-04-12

申请号：JP17827188

申请日：1988-07-19

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： KIN KOUSHIYU ,  SAI SOUKUN ,  GU YOUSHIYO ,  KIN JIYOKAN ,  RI SHINKOU

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

Abstract: PURPOSE: To ensure high speed and high integration characteristics by simultaneously fabricating a high speed bipolar transistor with self alignment of polycrystalline Si and a high integration CMOS device using one wafer. CONSTITUTION: The surface of a P type substrate (Si wafer) 1 is ion implanted with As using a buried layer mask to form N type buried layers 2, 3 and an N type epitaxial layer 4 is grown over the entire surface of the substrate. The layer 4 is ion implanted with B using an oxide film mask to form a P type well 5, and after the oxide film is formed, a Si3 N4 film is deposited. The inside of the layer 4 is ion implanted with B to form a P type junction isolation layer 6, and an oxide film is grown, and further a device isolation region 7 and an insulating layer 8 are formed. B, P are implanted using a mask to form a P type base region 9 and an N type collector region 10, and As is implanted to form an N type polycrystal Si layer 11 on which an oxide film 12 is deposited. Then, gates 13, 14, an emitter 15, and a collector 16 are simultaneously formed. Further, sources/drains 17, 18 and 19, 20 are formed.